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ADVANCE INFORMATION
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FEATURES
DDR3 Integrated Module [iMOD]: * Vcc=VccQ=1.5V 0.075V * 1.5V center-terminated, push/pull I/O * Package: 16mm x 12mm, 10 x 13 matrix w/ 129 balls * Matrix ball pitch: 1.00mm Space saving footprint Thermally enhanced, Impedance matched, integrated packaging Differential, bidirectional data strobe 8n-bit prefetch architecture 8 internal banks (per word, 2 words integrated in package) Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals. CAS (READ) latency (CL): 6, 8, and 10 CAS (WRITE) latency (CWL): 6, 7 and 8 Fixed burst length (BL) of 8 and burst chop (BC) of 4 Selectable BC4 or BL8 on-the-fly (OTF) Self/Auto Refresh modes Operating Temperature Range (Case Temp=Tc) * Industrial: -40C to 85C supporting SELF & AUTO REFRESH * Extended: -40C to 105C; manual REFRESH only * Mil-Temp: -55C to 125C; manual REFRESH only CORE clocking frequencies: * Industrial: 667MHz, 533MHz and 400MHz * Extended: 533MHz and 400MHz * Mil-Temp: 400MHz Data Transfer Rates: * Industrial: 1333, 1066 and 800 Mbps * Extended: 1066 and 800 Mbps * Mil-Temp: 800 Mbps Write leveling Multipurpose register Output Driver Calibration
Benefits
32% space savings while providing a surface mount friendly pitch (1.00mm) Reduced I/O routing (33%) 25% improvement in routings for your memory array Reduced trace lengths due to the highly integrated, impedance matched packaging Thermally enhanced packaging technology allow silicon integration without performance degradation due to power dissipation (heat) High TCE organic laminate interposer for improved glass stability over a wide operating temperature Suitability of use in High Reliability applications requiring Mil-temp, nonhermetic device operation
*Note: This integrated product is currently under consideration. Latest product status, information, and/ or corresponding documents should be obtained from LDI prior to your design consideration.
iMOD Part Information
ORDER NUMBER
L9D320G32BG6I25 L9D320G32BG6E25 L9D320G32BG6M25
SPEED GRADE
DDR3-1333 DDR3-1066 DDR3-800
DEVICE GRADE
Industrial Extended Mil-Temp
PKG FOOTPRINT
I/O
PITCH
PKG NO.
16mm x 12mm
129
1.00mm
BG2
integrated module products
LOGIC Devices Incorporated www.logicdevices.com 1
High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
ADVANCE INFORMATION
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
INTEGRATED VS. MONOLITHIC SOLUTIONS - HIGHLIGHTS
Monolithic Solu on O P T I O N S
Area I/O
IMOD Solu on
16.0
DDR3 9.0mm x 15.5mm 96 ball FBGA
DDR3 9.0mm x 15.5mm 96 ball FBGA
12.0
S A V I N G S
~32% 33%
2 x 139.5mm = 279mm PLUS 2 x 96 pins = 192 pins total
2
2
192 mm 2 129 Balls/Loca ons
TABLE 1: KEY TIMING PARAMETERS
Device Grade
INDUSTRIAL EXTENDED MIL-TEMP
Speed Grade
DDR3-1333 DDR3-1066 DDR3-800
Speed Mark
15 19 25
Part Ordering Information
L9D320G32BG6I15 L9D320G32BG6E19 L9D320G32BG6M25
CORE Freq. [MHz] Support
667/533/400 533/400 400
Data Rate [Mbps] Support
1333/1066/800 1066/800 800
Target
tRCD-tRP-CL
tRCD
tRP
CL [ns]
15 15 15
[ns]
15 15 15
[ns]
15 15 15
10-10-10/8-8-8/6-6-6 8-8-8/6-6-6 6-6-6
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
ADVANCE INFORMATION
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FEATURES FIGURE 1 - 1Gb DDR3 PART NUMBERS
Sample Part Number: L9D320G32BG6M15
L9D3
20G
32
BG6
DDR3 iMOD Total Density= 2.0Gb Organization= 64M x 32
Code 25 19 15
Speed Grade t CK = 2.50ns t CK = 1.875ns t CK = 1.5ns
16 x 12mm PBGA Temperature Industrial Temperature Extended Temperature Military Temperature Code I E M
Note: Not all options can be combined. Please see our Part Catalog for available offerings.
TABLE 2: ADDRESSING
Parameter
Configuration Refresh Count ROW Addressing Back Addressing Column Addressing
64 Meg x 64
[8 Meg x 8 banks x 16] x 2 8K 8K (A[12:0]) 8 (BA[2:0]) 1K (A[9:0])
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
ADVANCE INFORMATION
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
STATE DIAGRAM FIGURE 2 - SIMPLIFIED STATE DIAGRAM
CKE L
Power applied
Power on
Reset Procedure
Initialization
MRS, MPR, write leveling
SRE MRS SRX
Self refresh
ZQCL
From any state
RESET ZQ Calibration
ZQCL/ZQCS
REF
Idle
Refreshing
ACT
PDE PDX
Active PowerDown
PDX CKE L PDE
Activating
Preharge PowerDown
CKE L
Bank Active
WRITE WRITE WRITE AP READ AP READ WRITE READ READ
Writing
Reading
WRITE AP WRITE AP READ AP
READ AP
PRE, PREA
Writing
PRE, PREA
PRE, PREA
Reading
Preharging
Automatic Sequence Command Sequence
ACT = ACTIVATE MPR = Multipurpose register MRS = Mode register set PDE = Power-down entry PDX = Power-down exit PRE = PRECHARGE
PREA=PRECHARGE ALL READ = RD, RDS4, RDS8 READ AP = RDAP, RDAPS4, RDAPS8 REF = REFRESH RESET = START RESET PROCEDURE SRE = Self refresh entry
SRX = Self refresh exit WRITE = WR, WRS4, WRS8 WRITE AP = WRAP, WRAPS4, WRAPS8 ZQCL = ZQ LONG CALIBRATION ZQCS = ZQ SHORT CALIBRATION
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
ADVANCE INFORMATION
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FUNCTIONAL DESCRIPTION
The DDR3 SDRAM uses double data rate architecture to achieve high speed operation. The double data rate (DDR) architecture is an 8n prefetch with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE access for the DDR3 SDRAM consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal memory core and eight corresponding n-bit-wide, one-half-clock-cycle data transfer at the I/O pin. The differential strobes (LDQSx, LDQSx\, UDQSx, UDQSx\) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The READ data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. The DDR3 SDRAM operates from a differential clock (CKx, CKx\). The crossing of CK going HIGH and CK\ going LOW is referred to as the positive edge of Clock (CK). Control, Command, and Address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble. READ and WRITE accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and the starting column location for the burst access. DDR3 SDRAM devices use READ and WRITE BL8 and BC4. An AUTO PRECHARGE function may be enabled to provide a self-timed ROW PRECHARGE that is initiated at the end of the burst access. As with standard DDR SDRAM devices, the pipelined, multi-bank architecture of the DDR3 SDRAM allows for concurrent operation, thereby providing high bandwidth by hiding ROW PRECHARGE and ACTIVATION time. A SELF REFRESH mode is provided for all temperature grade offerings along with AUTO SELF REFRESH for Industrial product, as well as, powersaving, POWER-DOWN mode.
INDUSTRIAL TEMPERATURE
The industrial temperature (I) device requires the case temperature not exceed -40C or +85C. JEDEC specifications require the REFRESH rate to double when Tc exceeds +85C; this also requires use of the hightemperature SELF REFRESH option. Additionally, ODT resistance and the INPUT/OUTPUT impedance must be derated when the Tc is <0C or >+85C.
EXTENDED TEMPERATURE
The Extended temperature (E) device requires the case temperature not exceed -40C or +105C. JEDEC specifications require the refresh rate to double when Tc exceeds +85C; this also requires use of the hightemperature SELF REFRESH option. Additionally, ODT resistance and the INPUT/OUTPUT impedance must be derated when the Tc is <0C or >85C.
MILITARY, EXTREME OPERATING TEMPERATURE
The Mil-Temp (M) device requires the case temperature not exceed -55C or +125C. JEDEC requires the REFRESH rate double when Tc exceeds +85C and LDI recommends an additional derating as specified in this document as to properly maintain the DRAM core cell charge at temperatures above Tc>105C.
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
ADVANCE INFORMATION
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FIGURE 3 - FUNCTIONAL BLOCK DIAGRAM
CS\ RAS\ CAS\ CKE WE\ VCCQ VCC VSSQ VSS RESET\
A0-A12, BA0-1
A, BA RST\ VSS VSSQ VCC VCCQ WE\ CKE CAS\ RAS\ CS\
DQ 0
CK0 CK0\ LDQS0 LDQS0\ UDQS0 UDQS0\ LDM0 UDM0
DQ 0
D0
DQ 7 DQ 8
DQ 7 DQ 8
DQ 15
DQ 15
A, BA
RST\ VSS VSSQ VCC VCCQ WE\ CKE CAS\ RAS\ CS\
DQ 0
CK1 CK1\ LDQS1 LDQS1\ UDQS1 UDQS1\ LDM1 UDM1
DQ 16
D1
DQ 7 DQ 8
DQ 23 DQ 24
DQ 15
DQ 31
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
ADVANCE INFORMATION
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
BALL /SIGNAL LOCATION (PBGA) FIGURE 4 - SDRAM - DDR3 PINOUT TOP VIEW
1 A B C D E F G H J K L M N VSSQ VCC VCCQ VSS VSSQ ZQ0 VSSQ VSS VCCQ VCC VSSQ VSS 1
2 VCCQ DQ15 DQ3 DQ0 A4 A6 A0 A2 A8 DQ16 DQ19 DQ31 VCCQ 2
3 VSSQ DQ1 VSSQ DQ14 A10 RESET\ RAS\ NC A12 DQ30 VSSQ DQ17 VSSQ 3
4 VSS DQ13 VCCQ DQ2 A11 CK0 CS\ CK1\ A9 DQ18 VCCQ DQ29 VSS 4
5 VCC DQ7 LDQS0\ LDQS0 LDM0 VCC VrefCA VCC UDM1 UDQS1\ UDQS1 DQ23 VCC 5
6 VSS DQ8 UDQS0 UDQS0\ UDM0 VSS VrefDQ VSS LDM1 LDQS1 LDQS1\ DQ24 VSS 6
7 VCC DQ11 VCCQ DQ4 A1 CK0\ ODT CK1 A3 DQ20 VCCQ DQ27 VCC 7
8 VSSQ DQ5 VSSQ DQ10 A5 WE CAS\ CKE A7 DQ26 VSSQ DQ21 VSSQ 8
9 VCCQ DQ9 DQ12 DQ6 RFU/A14 BA0 RFU/A13 BA1 BA2 DQ22 DQ DQ25 VCCQ 9
10 VSS VSSQ VSS VCCQ VCC VSSQ ZQ1 VSSQ VCC VCCQ VSS VSSQ VSS 10 A B C D E F G H J K L M N
GND (Core) GND (I/O) Data I/O
V+ (Core Power) V+ (I/O Power) CNTRL
UNPOPULATED NC
Address DNU Level REF.
Rev.A, 7/09, 129BGA-1.00MM PITCH - X32
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
ADVANCE INFORMATION
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
TABLE 3 - BALL/SIGNAL LOCATION AND DESCRIPTION
Ball Assignments
G2, E7, H2, J7, E2, E8, F2, J8, J2, J4, E3, E4, J3
Symbol
A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10 /AP, A11, A12 /BC
Type
Description
address and auto precharge bit (A10) for READY/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW), bank selected by BA[2:0] or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to VrefCA. A12/BC#: when enabled in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop, LOW = BC4 burst chop).
Input Address Inputs: Provide the ROW address for ACTIVATE commands, and the column
F9, H9, J9
BA0, BA1, BA2
Input Bank Address Inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MRE, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to VrefCA.
G9, E9 F4, F7 H7, H4
RFU CKX, CKX\
Input Future Address: A13, A14 Input Clock: CKx and CKx\ are differential clock inputs, one differential pair per WORD, two WORDs contained in the L9D3xxG32 product. All control and address input signals are sampled on the crossing of the positive edge of CKx and the negative edge of CKx\. Output data strobes (UDQSx/UDQSx\ and LDQSx/LDQSx\) is referenced to the crossing of CKx and CKx\.
H8
CKE
Input Clock Enable: CKE enables and disables internal circuitry and clocks on the SDRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE power-down and SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is synchronous for power-down entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CKx, CKx\, CKE, RESET#, and ODT) are disabled during SELF REFRESH. CKE is referenced to VrefCA.
G4
CS\
Input Chip Select: CS\ enables (registered LOW) and disables the command decoder. All commands are masked when CS\ is registered HIGH. CS\ provides for external rank selection on systems with multiple ranks. CS\ is considered part of the command code. CS\ is referenced to VrefCA.
E5, E6 J6, J5
LDMx, UDMx
Input Input Data Mask: LDMx is the Lower-byte of a WORD, UDMx is the Upperbyte of a WORD, the L9D3xxG32 contains two WORDS. The data mask input, masks WRITE data. Lower byte data masked when LDMx is sampled HIGH, upper byte data masked when UDMx is sampled HIGH. The UDMx and LDMx pins are structured as inputs only, the pins electrical loading is designed to match that of the DQ and LDQSx\, UDQSx and UDQSx\ pins.
G3 G8 F8
RAS\ CAS\ WE\
Input ROW Address Strobe/Select: Defines the command being entered along CAS\, WE\, and CS\. This input pin is referenced to VrefCA. Input COLUMN Address Strobe/Select: Defines the command being entered along with RAS\, WE\, and CS\. This input pin is referenced to VrefCA. Input WRITE Enable Input: Defines the command being entered along with CAS\, RAS\,, and CS\. This input pin is referenced to VrefCA.
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
ADVANCE INFORMATION
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
TABLE 3 - BALL/SIGNAL LOCATION AND DESCRIPTION CONTINUED
Ball Assignments
G7
Symbol
Type
Description
Input On-Die Termination: ODT enables (when registered HIGH) and disables termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following signals: DQ[63:0], LDQSx, LDQSx\, UDQSx, UDQSx\, UDMx, and LDMx. The ODT input is ignored if disabled via the LOAD MODE register command. ODT is referenced to VrefCA.
ODT
F3
RESET\
Input RESET: An input control pin, active LOW referenced to Vss. The RESET\ input receiver is a CMOS input defined as a rail to rail signal with DC HIGH 0.8 x Vcc and DC LOW 0.2 x VccQ. RESET\ assertion and de-assertion are asynchronous.
D5, C5, K6, L6 C6, D6, L5, K5 D2, B3, D4 C2, D7, B8, D9, B5 B6, B9, D8, B7, C9, B4, D3, B2 K2, M3, K4, L2, K7, M8, K9, M5 M6, M9, K8, M7, L9, M4, K3, M2 A1
LDQSx, LDQSx\ UDQSx, UDQSx\ DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7 DQ8, DQ9, DQ10, DQ11, DQ12, DQ13, DQ14, DQ15 DQ16, DQ17, DQ18, DQ19, DQ20, DQ21, DQ22, DQ23 DQ24, DQ25, DQ26, DQ27, DQ28, DQ29, DQ30, DQ31 unpopulated
Input Data Strobe, LOW Byte (per WORD): Output, edge-aligned with READ data. Input, center-aligned with WRITE data. Input Data Strobe, HIGH Byte (per WORD): Output, edge-aligned with READ data. Input, center-aligned with WRITE data. I/O Data Input/Output: LOW Byte, LOW WORD (WORD 1). Pin referenced to VrefDQ.
I/O
Data Input/Output: HIGH Byte, LOW WORD (WORD 1). Pin referenced to VrefDQ.
I/O
Data Input/Output: LOW Byte, WORD 2. Pin referenced to VrefDQ.
I/O
Data Input/Output: HIGH Byte, WORD 2. Pin referenced to VrefDQ.
Unpopulated, un-plated matrix location(s)
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
ADVANCE INFORMATION
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FIGURE 5 - MECHANICAL DRAWING
11.97 12.05
12.00 NOM
129 x O 0.60 NOM
1.00 NOM
1.00 NOM 9.00 NOM
0.50 NOM
1.75 MAX
15.95 16.15
Note: All dimensions in mm
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
ADVANCE INFORMATION
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
TABLE 5: ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc VccQ VIN, VOUT TcIndustrial TcExtended TcMiltemp TSTG NOTES: 1. Vcc and VccQ must be within 300mV of each other at all times and VREF must not be greater than 0.6 x VccQ. When Vcc and VccQ are less than 500MV, VREF may be 300mV. 2. Max operating case temperature. Tc is measured in the center of the package. 3. Device Functionality is not guaranteed if the DRAM device exceeds the Maximum Tc during operation.
Parameter
Vcc Supply Voltage relative to Vss Vcc Supply Voltage relative to VssQ Voltage on any pin relative to Vss Operating Case Temperature Operating Case Temperature Operating Case Temperature Storage Temperature
MIN
-0.4 -0.4 -0.4 0 -40 -55 -55
MAX
1.975 1.975 1.975 85 105 125 120
UNITS
V V V C C C C
NOTES
1 1 1 2,3 2,3 2,3 2,3
TABLE 6: INPUT/OUTPUT CAPACITANCE
Capacitance Parameter
CK and CK\ C: CK to CK\ Single-end I/O: DQ, DM Differential I/O: DQS, DQS\ C: DQS to DQS\ C: DQ to DQS C: CNTL to CK C: cmd_ADDR to CK Inputs (RAS\, CAS\, WE\, CS\, CKE, ADDR) NOTES:
PACKAGE OUTLINE DIMENSIONS
DDR3-800 Symbol
CCK CDCK C10 C10 CCCQS CDI0 CDI_CNTL CDI_CMD_ADDR CI_Shared
DDR3-1066 MIN
3.1 0 1.5 1.5 0 -0.5 -0.5 -0.5 2.9
DDR3-1333 MIN
3.0 0 1.5 1.5 0 -0.5 -0.5 -0.5 2.9
MIN
3.1 0 1.5 1.5 0 -0.5 -0.5 -0.5 2.9
MAX
6.2 0.2 3.0 3.0 0.2 0.3 0.3 0.3 5.5
MAX
6.2 0.2 3.0 3.0 0.2 0.3 0.3 0.3 5.3
MAX UNITS NOTES
6.1 0.2 2.5 2.5 0.2 0.3 0.3 0.3 5.1 pF pF pF pF pF pF pF pF pF 2 3 3 4 6 7 5
1. Vcc = +1.5V 0.075mV, VccQ = Vcc, VREF = Vss, f= 100MHz, Tc = 25C, VOUT (DC) = 0.5 x VccQ, VOUT (peak to peak) = 0.1V 2. DM input is grouped with I/O pins, reflecting the signal is grouped with DQ and therefore matched in loading. 3. CCCQS is for DQS vs. DQS\ 4. CDIO = CIO (DQ) - 0.5 x (CIO [DQS] + CIO [DQS\]) 5. Excludes CK, CK\ 6. CDI_CNTL = CI(CNTL) - 0.5 x (CCK[CK] + CCK [CK\]); CNTL = ODT, CS\ and CKE 7. CDI_CMD_ADDR = CI (CMD_ADDR) - 0.5 x (CCK [CK] + CCK [CK\]); CMD = RAS\, CAS\, and WE\ ADDR = [n:0]
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
TABLE 8: TIMING PARAMETERS FOR ICC MEASUREMENTS - CLOCK UNITS
DDR3-800 -25 ICC Parameter
tCK
DDR3-1066 -19 8-8-8
1.875 8 8 28 20 8 27 6 59
DDR3-1333 -15 10-10-10
1.5 10 10 34 24 10 30 5 74
6-6-6
2.5 6 6 21 15 6 x32 x32 20 4 44
UNITS
ns CK CK CK CK CK CK CK CK
(MIN) ICC
CL ICC tRCD (MIN) ICC tRC (MIN) ICC tRAS (MIN) ICC tRP (MIN) ICC tFAW tRRD ICC tRFC
64M x 16 (2X)
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
High Performance, Integrated Memory Module Product
A [15:11] BA [2:0] A [9:7] A [10] RAS\ CAS\ ODT WE\
ADVANCE INFORMATION
Sub-Loop
CK, CK\
Command
Cycle Number
A [6:3]
A [2:0]
CKE
CS\
0
TABLE 9: ICC0 MEASUREMENT LOOP
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1 2 3 4 5 6 7
0 1 2 3 4 n RAS n RC n RC + 1 n RC + 2 n RC + 3 n RC + 4 n RC + n RAS 2 x nRC 4 x n RC 6 x n RC 8 x n RC 10 x n RC 12 x n RC 14 x n RC ACT D D D\ D\ 0 1 1 1 1 0 0 1 1 1 1 PRE 0 PRE ACT D D D\ D\
0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 Repeat cycles 1 through 4 until n RAS - 1, truncate if needed 0 1 0 0 0 0 0 0 0 Repeat cycles 1 through 4 until n RC - 1, truncate if needed 0 1 1 0 0 0 0 0 F 0 0 0 0 0 0 0 0 F 0 0 0 0 0 0 0 0 F 1 1 1 0 0 0 0 0 F 1 1 1 0 0 0 0 0 F Repeat cycles n RC +1 through n RC +4 until n RC - 1 + n RAS - 1, truncate if needed 0 1 0 0 0 0 0 0 F Repeat cycles n RC +1 through n RC +4 until 2 x RC - 1, truncate if needed Repeat sub-loop 0, use BA [2:0] = 1 Repeat sub-loop 0, use BA [2:0] = 2 Repeat sub-loop 0, use BA [2:0] = 3 Repeat sub-loop 0, use BA [2:0] = 4 Repeat sub-loop 0, use BA [2:0] = 5 Repeat sub-loop 0, use BA [2:0] = 6 Repeat sub-loop 0, use BA [2:0] = 7
0 0 0 0 0
0
Static HIGH
Toggling
0 0 0 0 0
Data
-
-
-
0
-
13
Jul 08, 2009 LDS-L9D320G32BG6-A
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
High Performance, Integrated Memory Module Product
A [15:11] BA [2:0] A [9:7] A [10] RAS\ CAS\ ODT WE\
0 0 0 1 1 1 0 0 0 0 1 1 1 0
ADVANCE INFORMATION
Sub-Loop
CK, CK\
Command
Cycle Number
A [6:3]
A [2:0]
CKE
0
0 1 2 3 4 n RCD n RAS n RC n RC +1 nRC +2 n RC +3 n RC +4 n RC + nRCD n RC + nRAS ACT D D D\ D\ 0 1 1 1 1 0 0 0 1 1 1 1 RD PRE 2 x n RC 2 x n RC 2 x n RC 2 x n RC 2 x n RC 2 x n RC 2 x n RC 0 0 RD PRE ACT D D D\ D\
CS\
TABLE 10: ICC1 MEASUREMENT LOOP
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1 2 3 4 5 6 7
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 Repeat cycles 1 through 4 until nRCD - 1, truncate if needed 0 1 0 0 0 0 0 0 Repeat cycles 1 through 4 until nRAS - 1, truncate if needed 1 0 0 0 0 0 0 0 Repeat cycles 1 through 4 until nRC - 1, truncate if needed 1 1 0 0 0 0 0 F 0 0 0 0 0 0 0 F 0 0 0 0 0 0 0 F 1 1 0 0 0 0 0 F 1 1 0 0 0 0 0 F Repeat cycles nRC + 1 through nRC + 4 until nRC + nRCD - 1, truncate if needed 0 1 0 0 0 0 0 F Repeat cycles nRC + 1 through nRC + 4 until nRC + nRAS - 1, truncate if needed 1 0 0 0 0 0 0 F Repeat cycle nRC + 1 through nRC + 4 until 2 x nRC - 1, truncate if needed Repeat sub-loop 0, use BA [2:0] = 1 Repeat sub-loop 0, use BA [2:0] = 2 Repeat sub-loop 0, use BA [2:0] = 3 Repeat sub-loop 0, use BA [2:0] = 4 Repeat sub-loop 0, use BA [2:0] = 5 Repeat sub-loop 0, use BA [2:0] = 6 Repeat sub-loop 0, use BA [2:0] = 7
0 0 0 0 0
0
00000000
0
Static HIGH
Toggling
0 0 0 0 0
Data
-
-
-
0
00110011
0
-
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Jul 08, 2009 LDS-L9D320G32BG6-A
L9D320G32BG6
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
TABLE 11: ICC MEASUREMENT CONDITIONS FOR POWER-DOWN CURRENTS
Icc2P0 Icc2P1 Icc2Q Precharge Power- Precharge PowerPrecharge Quiet Down Current Down Current Standby Current (Slow Exit) (Fast Exit)
n/a LOW Toggling tCK (MIN) ICC n\a n\a n\a n\a n\a n\a n\a HIGH LOW LOW LOW LOW Mid-level Enabled Enabled, OFF 8 None All n\a n/a LOW Toggling tCK (MIN) ICC n\a n\a n\a n\a n\a n\a n\a HIGH LOW LOW LOW LOW Mid-level Enabled Enabled, OFF 8 None All n\a n/a HIGH Toggling tCK (MIN) ICC n\a n\a n\a n\a n\a n\a n\a HIGH LOW LOW LOW LOW Mid-level Enabled Enabled, OFF 8 None All n\a
Name
Timing Pattern CKE External Clock tCK tRC tRAS tRCD tRRD tRC CL AL CS\ Command Inputs ROW/COLUMN Addr Bank Address DM Data I/O Output Buffer DQ, DQS ODT Burst Length ACTIVE Bank(s) IDLE Bank(s) Special Notes
Icc3P Active PowerDown Current
n/a LOW Toggling tCK (MIN) ICC n\a n\a n\a n\a n\a n\a n\a HIGH LOW LOW LOW LOW Mid-level Enabled Enabled, OFF 8 None All n\a
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
TABLE 12: ICC2N / ICC3N MEASUREMENT LOOP
Toggling Static HIGH
0 D D D\ D\ 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Repeat sub-loop 0, use BA [2:0] = 1 Repeat sub-loop 0, use BA [2:0] = 2 Repeat sub-loop 0, use BA [2:0] = 3 Repeat sub-loop 0, use BA [2:0] = 4 Repeat sub-loop 0, use BA [2:0] = 5 Repeat sub-loop 0, use BA [2:0] = 6 Repeat sub-loop 0, use BA [2:0] = 7 0 0 0 0 0 0 F F 0 0 0 0 1 2 3 4 5 6 7
CK, CK\ CKE Sub-Loop
0 1 2 3 4-7 8-11 12-15 16-19 20-23 24-27 28-31
Cycle Number
Command
CS\
RAS\
CAS\
WE\
ODT
BA [2:0]
A [15:11]
A [10]
A [9:7]
A [6:3]
A [2:0]
Data
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
High Performance, Integrated Memory Module Product
A [15:11] BA [2:0] A [9:7] A [10] RAS\ CAS\ ODT WE\
0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 Repeat sub-loop 0, use BA [2:0] = 1; ODT = 0 Repeat sub-loop 0, use BA [2:0] = 2; ODT = 1 Repeat sub-loop 0, use BA [2:0] = 3; ODT = 1 Repeat sub-loop 0, use BA [2:0] = 4; ODT = 0 Repeat sub-loop 0, use BA [2:0] = 5; ODT = 0 Repeat sub-loop 0, use BA [2:0] = 6; ODT = 1 Repeat sub-loop 0, use BA [2:0] = 7; ODT = 1 0 0 0 0
ADVANCE INFORMATION
Sub-Loop
Command
CK, CK\
Cycle Number
A [6:3]
A [2:0]
CKE
0
1 2 3 4 5 6 7
0 1 2 3 4-7 8-11 12-15 16-19 20-23 24-27 28-31
Static HIGH
Toggling
TABLE 13: ICC2NT MEASUREMENT LOOP
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D D D\ D\
CS\
1 1 1 1
0 0 F F
0 0 0 0
Data
-
Jul 08, 2009 LDS-L9D320G32BG6-A
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
High Performance, Integrated Memory Module Product
A [15:11] BA [2:0] A [9:7] A [10] RAS\ CAS\ ODT WE\
1 0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Repeat sub-loop 0, use BA [2:0] = 1 Repeat sub-loop 0, use BA [2:0] = 2 Repeat sub-loop 0, use BA [2:0] = 3 Repeat sub-loop 0, use BA [2:0] = 4 Repeat sub-loop 0, use BA [2:0] = 5 Repeat sub-loop 0, use BA [2:0] = 6 Repeat sub-loop 0, use BA [2:0] = 7 0 0 0 0 0 0 0 0
ADVANCE INFORMATION
Sub-Loop
CK, CK\
Command
Cycle Number
A [6:3]
A [2:0]
CKE
0
TABLE 14: ICC4R MEASUREMENT LOOP
1 2 3 4 5 6 7
0 1 2 3 4 5 6 7 8-15 16-23 24-31 32-39 40-47 48-55 56-63 RD D D\ D\ RD D D\ D\
CS\
Static HIGH
Toggling
0 1 1 1 0 1 1 1
0 0 0 0 F F F F
0 0 0 0 0 0 0 0
00000000 00110011 -
Data
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Jul 08, 2009 LDS-L9D320G32BG6-A
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
High Performance, Integrated Memory Module Product
A [15:11] BA [2:0] A [9:7] A [10] RAS\ CAS\ WE\ ODT
1 0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 Repeat sub-loop 0, use BA [2:0] = 1 Repeat sub-loop 0, use BA [2:0] = 2 Repeat sub-loop 0, use BA [2:0] = 3 Repeat sub-loop 0, use BA [2:0] = 4 Repeat sub-loop 0, use BA [2:0] = 5 Repeat sub-loop 0, use BA [2:0] = 6 Repeat sub-loop 0, use BA [2:0] = 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADVANCE INFORMATION
Sub-Loop
CK, CK\
Command
Cycle Number
A [6:3]
A [2:0]
CKE
Sta c HIGH
Toggling
TABLE 15: ICC4W MEASUREMENT LOOP
1 2 3 4 5 6 7
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0
0 1 2 3 4 5 6 7 8-15 16-23 24-31 32-39 40-47 48-55 56-63
WR D D\ D\ WR D D\ D\
CS\
0 1 1 1 0 1 1 1
0 0 0 0 F F F F
0 0 0 0 0 0 0 0
00000000 00110011 -
Data
Jul 08, 2009 LDS-L9D320G32BG6-A
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
High Performance, Integrated Memory Module Product
A [15:11] BA [2:0] A [9:7] A [10] RAS\ CAS\ ODT WE\
Repeat sub-loop 1a, use BA [2:0] = 1 Repeat sub-loop 1a, use BA [2:0] = 2 Repeat sub-loop 1a, use BA [2:0] = 3 Repeat sub-loop 1a, use BA [2:0] = 4 Repeat sub-loop 1a, use BA [2:0] = 5 Repeat sub-loop 1a, use BA [2:0] = 6 Repeat sub-loop 1a, use BA [2:0] = 7 Repeat sub-loop 1a through 1h until n RFC - 1, truncate if needed
ADVANCE INFORMATION
Sub-Loop
CK, CK\
Command
Cycle Number
A [6:3]
A [2:0]
CKE
0 1a
1b 1c 1d 1e 1f 1g 1h 2
0 1 2 3 4 5-8 9-12 13-16 17-20 21-24 25-28 29-32 33-n RFC-1
TABLE 16: ICC5B MEASUREMENT LOOP
Static HIGH
Toggling
REF D D D\ D\
CS\
Data
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Jul 08, 2009 LDS-L9D320G32BG6-A
L9D320G32BG6
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L9D320G32BG6
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TABLE 17: ICC MEASUREMENT LOOP
Industrial Range Tc =-40C to 85C
PACKAGE OUTLINE DIMENSIONS
Extended or Mil Temperature Range, Tc = -40C to 85C or -55C to 125C
ICC Test
CKE External Clock
tCK tRC tRAS tRCD tRRD
Icc6: Self Refresh Current
LOW Off, CK and CK\ = LOW n\a n\a n\a n\a n\a n\a n\a n\a Mid-level Mid-level Mid-level Mid-level Mid-level Enabled Enabled, Mid-level n\a n\a n\a Disabled (normal) Disabled
Icc6E/M: Self Refresh Current
LOW Off, CK and CK\ = LOW n\a n\a n\a n\a n\a n\a n\a n\a Mid-level Mid-level Mid-level Mid-level Mid-level Enabled Enabled, Mid-level n\a n\a n\a Enabled (extended) Disabled
Icc8: Reset
Mid-level Mid-level n\a n\a n\a n\a n\a n\a n\a n\a Mid-level Mid-level Mid-level Mid-level Mid-level Mid-level Mid-level n\a None All n\a n\a
tRC CL AL CS\ Command Inputs ROW/COLMUN addresses BANK addresses Data I/O Output buffer DQ, DQS ODT Burst Length Active BANKS IDLE BANKS SRT ASR
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
High Performance, Integrated Memory Module Product
A [15:11] BA [2:0] A [9:7] A [10] RAS\ CAS\ ODT WE\ CS\
0 0 1 0 0 1 0 1 0 0 1 0 1 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 Repeat cycle 2 until n RRD - 1 1 1 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 0 0 Repeat cycle n RRD + 2 until 2 x n RRD - 1 Repeat sub-loop 0, use BA[2:0] = 2 Repeat sub-loop 0, use BA[2:0] = 3 0 0 0 3 0 0 0 Repeat cycle 4 x n RRD until n FAW - 1, if needed Repeat sub-loop 0, use BA[2:0] = 4 Repeat sub-loop 1, use BA[2:0] = 5 Repeat sub-loop 0, use BA[2:0] = 6 Repeat sub-loop 1, use BA[2:0] = 7 0 0 0 7 0 0 0 Repeat cycle n FAW + 4 x n RRD until 2 x n FAW - 1, if needed 1 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 Repeat cycle 2 x n FAW + 2 until 2 x n FAW + n RRD - 1 1 1 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 0 0 Repeat cycle 2 x n FAW + n RRD + 2 until 2 x n FAW + 2 x n RRD - 1 Repeat sub-loop 10, use BA[2:0] = 2 Repeat sub-loop 11, use BA[2:0] = 3 0 0 0 3 0 0 0 Repeat cycle 2 x n FAW + 4 x n RRD until 3 x n FAW - 1, if needed Repeat sub-loop 10, use BA[2:0] = 4 Repeat sub-loop 11, use BA[2:0] = 5 Repeat sub-loop 10, use BA[2:0] = 6 Repeat sub-loop 11, use BA[2:0] = 7 0 0 0 7 0 0 0 Repeat cycle 3 x n FAW + 4 x n RRD until 4 x n FAW - 1, if needed
ADVANCE INFORMATION
Sub-Loop
CK, CK\
Command
Cycle Number
A [6:3]
A [2:0]
CKE
0 ACT RDA D
1 2 3 4 5 6 7 8 9 D ACT RDA D ACT RDA D D
10
11 12 13 14 15 16 17 18 19
TABLE 18: ICC7 MEASUREMENT LOOP
0 1 2 3 n RRD n RRD + 1 n RRD + 2 n RRD + 3 2 x n RRD 3x n RRD 4 x n RRD 4 x n RRD + 1 n FAW n FAW + n RRD n FAW + 2xn RRD n FAW + 3xn RRD n FAW + 4xn RRD n FAW + 4xn RRD+1 2 x n FAW 2 x n FAW + 1 2 x n FAW + 2 2 x n FAW + 3 2 x n FAW + n RRD 2 x n FAW + n RRD+1 2 x n FAW + n RRD+2 2 x n FAW + n RRD+3 2 x nFAW + 2x n RRD 2 x n FAW + 3x n RRD 2 x n FAW + 4x n RRD 2 x n FAW+4x n RRD+1 3 x nFAW 3 x nFAW + nRRD 3 x nFAW + 2x nRRD 3 x nFAW + 3x nRRD 3 x nFAW + 4x nRRD 3 x nFAW + 4x nRRD +1
ACT RDA D
0 0 0
0 0 0
00000000 -
F F F
0 0 0
00110011 -
F
0
Data
-
Static HIGH
Toggling
F
0
-
F F F
0 0 0
00110011 -
0 0 0
0 0 0
00000000 -
D
0
0
-
D
0
0
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Jul 08, 2009 LDS-L9D320G32BG6-A
L9D320G32BG6
ADVANCE INFORMATION
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
TABLE 19: ICC MAXIMUM LIMITS
Speed Bin ICC
Icc0 IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP
DDR3-800
175 183 190 217 232 240 23 30 88 59 76 88 92 120 137 98 126 145 157 203 232 59 61 65 98 100 108 450 460 470 471 480 7/8/2009 392 400 408 12 21 38 686 737 795 ICC2P + 2mA ICC2P + 2.1mA ICC2P + 2.4mA
3.
DDR3-1066
195 203 255 265 23 30 69 89 105 137 107 139 186 242 69 73 107 109 510 520 568 580 430 440 12 21 745 800 ICC2P + 2mA ICC2P + 2.1mA
DDR3-1333
218
UNITS
mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
Notes
1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3
Icc1
292
Icc2P0
23
Icc2P1
78
Icc2Q
120
Icc2N
128
Icc2NT
205
Icc3P
78
Icc3N
118
Icc4R
568
Icc4W
696
Icc5B
470
Icc6
12
Icc7
823
Icc8
ICC2P + 2mA
NOTES: 1. 2. Tc = 0C to 85C; SRT and ASR are disabled, enabling ASR could increase ICCx by up to an additional 2mA. Tc = -40C to 105C; SRT and ASR are disabled, enabling ASR could increase ICCx by up to an additional 2mA. Tc = -55C to 125C; SRT and ASR are disabled, enabling ASR could increase ICCx by up to an additional 2mA.
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
ADVANCE INFORMATION
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
TABLE 20: DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS PACKAGE OUTLINE DIMENSIONS
All Voltages are referenced to Vss
Parameter/Condition
Supply Voltage I/O Supply Voltage Input Leakage Current: Any input 0VVINVcc, VREF pin 0VVIN1.1V All other pins not under test = 0V VREF Supply Leakage Current: VREFDQ = Vcc/2 or VREFCA = Vcc/2 All other pins not under test = 0V NOTES: 1.
Symbol
Vcc VccQ II
MIN
1.425 1.425 -2
TYP
1.5 1.5 -
MAX
1.575 1.575 2
UNITS
V V A
NOTES
1,2 1,2
IVREF
-1
-
1
A
3,4
Vcc and VccQ must track one another, VccQ must be less than or equal to Vcc, Vss = VssQ.
3. 4.
VREF (see Table 22). The minimum limit requirement is for testing purposes. The leakage current on the VREF pin should be minimal.
2.
Vcc and VccQ may include AC noise of 50mV (250 kHz to 20MHz) in addition to the DC (0Hz to 250kHz) specifications, Vcc and VccQ must be at the same level for valid AC timing parameters.
TABLE 21: DC ELECTRICAL CHARACTERISTICS AND INPUT CONDITIONS OUTLINE DIMENSIONS PACKAGE
All Voltages are referenced to Vss
Parameter/Condition
VIN low; DC/commands/address busses VIN high; DC/commands/address busses Input reference voltage command/address bus I/O reference voltage DQ bus I/O reference voltage DQ bus in SELF REFRESH Command/address termination voltage (system level, not direct DRAM input) NOTES: 1.
Symbol
VIL VIH VREFCA(DC) VREFDQ(DC) VREFDQ(SR) VTT
MIN
Vss
See Table 20
TYP
n/a n/a 0.5 x Vcc 0.5 x Vcc 0.5 x Vcc 0.5 x VccQ
MAX
See Table 20
UNITS
V V V V V V
NOTES
Vcc 0.51 x Vcc 0.51 x Vcc Vcc
-
0.49 x Vcc 0.49 x Vcc Vss
-
1,2 2,3 4 5
VREFCA(DC) is expected to be approximately 0.5 x Vcc and to track variations in the DC level. Externally generated peak noise (noncommon mode) on VREFCA may not exceed 1% x Vcc around the VREFCA(DC) value. Peak-to-peak AC noise on VREFCA should not exceed 2% of VREFCA(DC). 4.
mon mode) on VREFDQ may not exceed 1% x Vcc around the VREFDQ(DC) value. Peak-to-peak AC noise on VREFDQ should not exceed 2% of VREFDQ(DC). VREFDQ(DC) may transition to VREFDQ(SR) and back to VREFDQ(DC) when in SELF zREFRESH, within restrictions outlined in the SELF REFRESH section. 5. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors. MIN and MAX values are system-dependent.
2.
DC values are determined to be less than 20MHz in frequency. DRAM must meet specifications if the DRAM induces additional AC noise greater than 20MHz in frequency.
3.
VREFDQ(DC) is expected to be approximately 0.5 x Vcc and to track variations in the DC level. Externally generated peak noise (noncom-
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
TABLE 22: INPUT SWITCHING CONDITIONS
Parameter/Condition
Command and Address
Input high AC voltage: Logic 1 Input high AC voltage: Logic 1 Input high DC voltage: Logic 1 Input high DC voltage: Logic 0 Input high AC voltage: Logic 0 Input high AC voltage: Logic 0 VIH (AC175) MIN VIH (AC150) MIN VIH (DC100) MIN VIL (DC100) MAX VIL (AC150) MAX VIL (AC175) MAX +175 +150 +100 -100 -150 -175 +175 +150 +100 -100 -150 -175 mV mV mV mV mV mV
PACKAGE OUTLINE DIMENSIONS
Symbol DDR3-1066 DDR3-900 DDR1333 UNITS
DQ and DM
Input high AC voltage: Logic 1 Input high AC voltage: Logic 1 Input high DC voltage: Logic 1 Input high DC voltage: Logic 0 Input high AC voltage: Logic 0 Input high AC voltage: Logic 0 NOTES: 1. All voltages are referenced to VREF, VREF is VREFCA for control, command, and address. All slew rates and setup/hold times are specified at the DRAM ball. VREF is VREFDQ for DQ and DM inputs. 4. 2. Input setup timing parameters (tIS and tDS) are referenced at VIL(AC)/ VIH(AC), not VREF(DC). Single-ended input slew rate = 1V/ns; maximum input voltage swing under test is 900mV (peak-to-peak). 3. Input hold timing parameters (tIH and tDH) are referenced at VIL(DC)/ VIH(DC), not VREF(AC). VIH (AC175) MIN VIH (AC150) MIN VIH (DC100) MIN VIL (DC100) MAX VIL (AC150) MAX VIL (AC175) MAX +175 +150 +100 -100 -150 -175 +150 +100 -100 -150 mV mV mV mV mV mV
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
OPERATING CONDITIONS FIGURE 6 - INPUT SIGNAL
VIL and VIH levels with ringback 1.90V
VDDQ + 0.4V narrow pulse width
1.50V Minimum VIL and VIH levels VIH (AC) 0.925V
VDDQ
0.925V
VIH (AC)
VIH (DC) 0.850V 0.850V
VIH (DC)
0.780V 0.765V 0.750V 0.735V 0.720V
0.780V 0.765V 0.750V 0.735V 0.720V
VREF + AC noise VREF + DC error VREF + DC error VREF + AC noise
0.650V
VIL (DC)
0.650V
VIL (DQ)
0.575V VIL (AC)
0.575V
VIL (AC)
0.0V
VSS
-0.40V
VSS 0.4V narrow pulse width
Notes:
1. Numbers in diagrams reflect nominal values.
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
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AC OVERSHOOT/UNDERSHOOT SPECIFICATION TABLE 23: CONTROL AND ADDRESS PINS
Parameter
Maximum peak amplitude allowed for overshoot area (see Figure 16 on page 38) Maximum peak amplitude allowed for overshoot area (see Figure 17 on page 39) Maximum overshoot area above Vcc (see Figure 16 on page 38) Maximum undershoot area below Vss (see Figure 17 on page 39) 0.67Vns 0.67Vns 0.5Vns 0.5Vns 0.4Vns 0.4Vns 0.4V 0.4V 0.4V
PACKAGE OUTLINE DIMENSIONS
DDR3-800
0.4V
DDR3-1066
0.4V
DDR3-1333
0.4V
TABLE 24: CLOCK, DATA, STROBE, AND MASK PINS
Parameter
Maximum peak amplitude allowed for overshoot area (see Figure 16 on page 38) Maximum peak amplitude allowed for overshoot area (see Figure 17 on page 39) Maximum overshoot area above Vcc/ VccQ (see Figure 16 on page 38) Maximum undershoot area below Vss/ VssQ (see Figure 17 on page 39)
PACKAGE OUTLINE DIMENSIONS
DDR3-800
0.4V
DDR3-1066
0.4V
DDR3-1333
0.4V
0.4V
0.4V
0.4V
0.25Vns
0.19Vns
0.15Vns
0.25Vns
0.19Vns
0.15Vns
FIGURE 7 & 8: OVERSHOOT/UNDERSHOOT SPECIFICATIONS
Volts (V)
Maximum amplitude
Overshoot area
Figure 7: Overshoot
VCC/VCCQ Time (ns)
Time (ns)
Figure 8: Undershoot
VSS/VSSQ
Volts (V) Maximum amplitude
Undershoot area
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TABLE 25: DIFFERENTIAL INPUT OPERATING CONDITIONS (CKX, CKX\, DQSX, AND DQSX\) PACKAGE OUTLINE DIMENSIONS
Parameter/Condition
Differential input voltage, logic high - slew Differential input voltage, logic low - slew Differential input voltage, logic high Differential input voltage, logic low Differential input crossing voltage relative to Vcc/2 for DQS, DQS\, CK, CK\ Differential input crossing voltage relative to Vcc/2 for CK, CK\ Single-ended high level for strobes Single-ended high level for CK, CK\ Single-ended low level for strobes Single-ended low level for CK, CK\ NOTES: 1. Clock is referenced to VccD and Vss. Data strobe is referenced to VccQ and VssQ. 2. 3. 4. 5. Reference is VREFCA(DC) for clock and for VREFDQ(DC) for strobe. Differential input slew rate = 2V/ms. Defines slew rate reference points relative to input crossing voltages. 8. MAX limit is relative to single-ended signals, the overshoot specifications are applicable. The VIX extended range (175mV) is allowed only for the clock and this VIX extended range is only allowed when the following conditions are met: The single-ended input signals are monotonic, have the singleended swing VSEL, VSEH of at least Vcc/2 250mV, and the differential slew rate of CK, CK\ is greater than 3V/ns. 7. 6. MIN limit is relative to single-ended signals, the undershoot specifications are applicable. The typical value of VIX(AC) is expected to be about 0.5 x Vcc of the transmitting device and VIX(AC) is expected to track variations in Vcc. VIX(AC) indicates the voltage at which differential input signals must cross. VSEL VSHE VccQ/2 + VIH(AC) Vcc/2 + VIH(AC VssQ Vss VccQ Vcc VccQ/2-VIL(AC) Vcc/2-VIL(AC) mV 6 mV 5 VIX(175) VREF(DC) - 175 VREF(DC) + 175 mV 7,8
Symbol
VIH DIFF(AC)slew VIL DIFF(AC)slew VIH DIFF(AC) VIL DIFF(AC) VIX
MIN
+200 n/a 2x(VIH(AC)-VREF) Vss/VssQ VREF(DC) - 150
MAX
n/a -200 Vcc/VccQ 2x(VREF-VIL(AC)) VREF(DC) + 150
UNITS
mV mV mV mV mV
NOTES
4 4 5 6 7
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
OVERSHOOT/UNDERSHOOT SPECIFICATIONS FIGURE 9 - VIX FOR DIFFERENTIAL SIGNALS
VCC, VCCQ CK#, DQS# X VIX VCC/2, VCCQ/2 X VCC/2, VCCQ/2 VIX X CK, DQS VSS, VSSQ VIX CK, DQS VSS, VSSQ VCC, VCCQ CK#, DQS# VIX
X
FIGURE 10 - SINGLE-ENDED REQUIREMENTS FOR DIFFERENTIAL SIGNALS
VCC or VCC Q
VSEH (MIN)
VCC /2 or VCC Q/2 VSEH VSEL (MAX) CK or DQS
VSEL VSS or VSS Q
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
OVERSHOOT/UNDERSHOOT SPECIFICATIONS FIGURE 11 - DEFINITION OF DIFFERENTIAL AC-SWING AND tDVAC
t DVAC V IHDIFF (AC) MIN
V IHDIFF (MIN) V IHDIFF (DC) MIN CK - CK# DQ S - DQS # 0.0
V ILDIFF (DC) MAX V ILDIFF (MAX)
V ILDIFF (AC) MAX half cycle t DVAC
TABLE 26: DIFFERENTIAL INPUT OPERATING CONDITIONS (tDVAC) FOR CKX, CKX\, DQSX, AND DQSX\ PACKAGE OUTLINE DIMENSIONS
Below VIL (AC)
tDVAC (ps) at [VIHDIFF(AC) to VILDiff(AC)] Slew Rate (V/ns)
-4.0 4.0 3.0 2.0 1.9 1.6 1.4 1.2 1.0 <1.0
350mV
75 57 50 38 34 29 22 13 0 0
300mV
175 170 167 163 162 161 159 155 150 150
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
SLEW RATE DEFINITIONS FOR SINGLE-ENDED INPUT SIGNALS
Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew-rate between the last crossing of VREF and the first crossing VIH(AC) MIN. Setup (tIS and tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF an the first crossing of VIL(AC) MAX. Hold (tIH and tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC) MAX and the first crossing of VREF. Hold (tIH and tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC) MIN and the first crossing of VREF.
TABLE 27: SINGLE-ENDED INPUT SLEW RATE
Input Slew Rate (Linear Signals) Input Edge
Rising Setup Falling VREF
PACKAGE OUTLINE DIMENSIONS
Measured To
VIH(AC)MIN
From
VREF
Calculation
VIH(AC) MIN - VREF VREF - VIL(AC) MAX TFS VREF - VIL(DC) MAX TFH
VIL(AC)MAX
Rising Hold Falling
VIL(DC)Max
VREF
VIH(DC)MIN
VREF
VIH(DC) MIN - VREF TRSH
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
SLEW RATE DEFINITIONS FOR SINGLE-ENDED INPUT SIGNALS FIGURE 12 - NOMINAL SLEW RATE DEFINITION FOR SINGLE-ENDED INPUT SIGNALS
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
SLEW RATE DEFINITIONS FOR DIFFERENTIAL INPUT SIGNALS
Input slew rate for differential signals (CKx, CKx\, UDQSx , UDQSx\, LDQSx and LDQSx\) are defined and measured as shown in Table 28. The nominal slew rate for a rising signal is defined as the slew rate between VIL(DIFF) MAX and VIH(DIFF) MIN. The nominal slew rate for a falling signal is defined as the slew rate between VIH(DIFF) MIN and VIL(DIFF) MAX.
TABLE 28: DIFFERENTIAL INPUT SLEW RATE DEFINITION
Input Slew Rate (Linear Signals) Input
CK and DQS Reference Falling VREF
PACKAGE OUTLINE DIMENSIONS
To
VIH(AC)MIN
Measured From
VREF
Edge
Rising
Calculation
VIH(DIFF) MIN - VIL(DIFF) MAX TR(DIFF) VIH(DIFF) MIN - VIL(DIFF) MAX
VIL(AC)MAX
TF(DIFF)
FIGURE 13 - NOMINAL DIFFERENTIAL INPUT SLEW RATE DEFINITION FOR DQS, DQS# AND CK, CK#
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
ODT CHARACTERISTICS
ODT's effective resistance RTT is defined by MR1[9,6 and 2]. ODT is applied to the DQx, UDMx, LDMx, UDQSx, UDQSx\, LDQSx and LDQSx\ balls. The ODT target values are listed in Table 29.
FIGURE 14 - ODT LEVELS AND I-V CHARACTERISTICS
Chip in termination mode ODT VCCQ IPU IOUT = IPD - IPU To other circuitry such as RCV, . . . RTTPU DQ IOUT RTTPD IPD VSSQ VOUT
TABLE 29: ON-DIE TERMINATION DC ELECTRICAL CHARACTERISTICS
Parameter/Condition
RTT effective impedance Deviation of VM with respect to VccQ/2 NOTES: 1. Tolerance limits are applicable after a proper ZQ calibration has been performed at a stable temperature and voltage (VccQ=Vcc, VssQ-Vss). Refer to "ODT Sensitivity" on page 37 if either the temperature or voltage changes after calibration. 2. Measurement definition for RTT: Apply VIH(AC) to a pin under test and measure the current I[VIH(AC)], then apply VIL(AC) to pin under test and measure current I[VIL(AC)]: VIL(AC) - VIL(AC) RTT = I[VIH(AC))-I(VIL(AC))] 4. For extended MIL-temp devices, the minimum values are derated by 6% when the device is between -40C and 0C (Tc). VM = 2 x VM VccQ -1 x 100 3. Measure voltage (VM) at the tested pin with no load:
Symbol
RTT_EFF VM
MIN
-5
TYP
MAX
5
UNITS
%
NOTES
1, 2, 4 1, 2, 3, 4
See Table 30
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Jul 08, 2009 LDS-L9D320G32BG6-A
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TABLE 30: RTT EFFECTIVE IMPEDANCES
MR1 [9,6,2]
RTT Resistor
RTT120PD240 0, 1, 0 120 RTT120PU240
PACKAGE OUTLINE DIMENSIONS
VOUT
0.2 x VccQ 0.5 x VccQ 0.8 x VccQ 0.2 x VccQ 0.5 x VccQ 0.8 x VccQ
MIN
0.6 0.9 0.9 0.9 0.9 0.9 0.9 0.6 0.9 0.9 0.9 0.9 0.9 0.9 0.6 0.9 0.9 0.9 0.9 0.9 0.9 0.6 0.9 0.9 0.9 0.9 0.9 0.9 0.6 0.9 0.9 0.9 0.9 0.9 0.9
TYP
1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0
MAX
1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6
UNITS
RZQ/1 RZQ/1 RZQ/1 RZQ/1 RZQ/1 RZQ/1 RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/4 RZQ/3 RZQ/3 RZQ/3 RZQ/3 RZQ/3 RZQ/3 RZQ/6 RZQ/4 RZQ/4 RZQ/4 RZQ/4 RZQ/4 RZQ/4 RZQ/8 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/12
120
VIL(AC) to VIH(AC) 0.2 x VccQ RTT60PD120 0.5 x VccQ 0.8 x VccQ 0.2 x VccQ RTT60PU240 0.5 x VccQ 0.8 x VccQ
0, 0, 1
60
60
VIL(AC) to VIH(AC) 0.2 x VccQ RTT40PD80 0.5 x VccQ 0.8 x VccQ 0.2 x VccQ RTT40PU80 0.5 x VccQ 0.8 x VccQ
0, 1, 1
40
40
VIL(AC) to VIH(AC) 0.2 x VccQ RTT30PD60 0.5 x VccQ 0.8 x VccQ 0.2 x VccQ RTT30PU60 0.5 x VccQ 0.8 x VccQ
1, 0, 1
30
30
VIL(AC) to VIH(AC) 0.2 x VccQ RTT20PD40 0.5 x VccQ 0.8 x VccQ 0.2 x VccQ RTT20PU40 0.5 x VccQ 0.8 x VccQ
1, 0, 0
20
20
VIL(AC) to VIH(AC)
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
ADVANCE INFORMATION
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
ODT SENSITIVITY
If either the temperature or voltage changes after I/O calibration, the tolerance limits listed in Table 29 can be expected to widen according to Tables 31 and 32.
TABLE 31: ODT SENSITIVITY DEFINITION
Symbol
RTT
MIN
0.9 - dRTTdT x dRTTdV x [DV]
MAX
1.6 + dRTTdT x [DT] + dRTTdV x [DV]
UNITS
RZQ/(2, 4, 6, 8, 12)
TABLE 32 - ODT TEMPERATURE & VOLTAGE SENSITIVITY
Change
dRTTdT dRTTdV
MIN
0 0
MAX
1.5 0.15
UNITS
0 0
ODT TIMING DEFINITIONS
ODT loading differs from that used in AC timing measurements. Two parameters define when ODT turns on or off synchronously, two define when ODT turns on or off Asynchronously and, another defines when ODT turns on or off dynamically. Table 33 outlines and provides definition and measurement reference settings for each parameter. ODT turn-on time begins when the output leaves HIGH-Z and ODT resistance begins to turn on. ODT turn-off time begins when the output leaves LOW-Z and ODT resistance begins to turn-off.
FIGURE 15 - ODT TIMING REFERENCE LOAD
VREF VCCQ/2 RTT = 25 VTT = VSSQ Timing reference point RZQ = 240 VSSQ
DUT CK, CK#
DQ, DM DQS, DQS# ZQ
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
ADVANCE INFORMATION
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
ODT TIMING DEFINITIONS TABLE 33: ODT TIMING DEFINITIONS
Symbol
tAON tAOF tAONPD tAOFPD tADC
PACKAGE OUTLINE DIMENSIONS
End Point Definition
Extrapolated point at VssQ Extrapolated point at VRTT_NORM Extrapolated point at VssQ Extrapolated point at VRTT_NOM Extrapolated points at VRTT_WR and VRTT_NOM
Begin Point Definition
Rising edge of CK-CK\ defined by the end point of ODTL on Rising edge of CK-CK\ defined by the end point of ODTL off Rising edge of CK-CK\ with ODT first being registered HIGH Rising edge of CK-CK\ with ODT first being registered LOW Rising edge of CK-CK\ defined by the end point of ODTLCNW, ODTLCWN4, or ODTLCWN8
Figure
Figure 25 on page 60 Figure 25 on page 60 Figure 26 on page 61 Figure 26 on page 61 Figure 27 on page 62
TABLE 34: REFERENCE SETTINGS FOR ODT TIMING MEASUREMENTS PACKAGE OUTLINE DIMENSIONS
Measured Parameter
tAON tAOF tAONPD tAOFPD tADC
RTT_NORM Setting
RZQ/4 (60) RZQ/12 (20) RZQ/4 (60) RZQ/12 (20) RZQ/4 (60) RZQ/12 (20) RZQ/4 (60) RZQ/12 (20) RZQ/12 (20)
RTT_WR_Setting
n/a n/a n/a n/a n/a n/a n/a n/a RZQ/2 (120)
VSW1
50mV 100mV 50mV 100mV 50mV 100mV 50mV 100mV 200mV
VSW2
100mV 200mV 100mV 200mV 100mV 200mV 100mV 200mV 300mV
FIGURE 16 - tAON AND tAOF DEFINITIONS
t AON Begin point: Rising edge of CK - CK# defined by the end point of ODTL on CK CK VCCQ/2 CK# t AON CK# t AOF End point: Extrapolated point at VRTT_NOM TSW2 TSW1 TSW1 TSW1 DQ, DM DQS, DQS# VSSQ VSW1 End point: Extrapolated point at VSSQ VSW2 VSW2 VSW1 VSSQ VRTT_NOM t AOF Begin point: Rising edge of CK - CK# defined by the end point of ODTL off
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
ADVANCE INFORMATION
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
ODT CHARACTERISTICS FIGURE 17 - tAONPD AND tAOFPD DEFINITION
t AONPD Begin point: Rising edge of CK - CK# with ODT first registered HIGH CK CK
t AOFPD Begin point: Rising edge of CK - CK# with ODT first registered LOW
VCCQ/2 CK# t AONPD CK# t AOFPD End point: Extrapolated point at VRTT_NOM TSW2 TSW2 TSW1 TSW1 VSW2 DQ, DM DQS, DQS# VSSQ VSW1 VSW2 VSW1 VSSQ End point: Extrapolated point at VSSQ VRTT_NOM
FIGURE 18 - tADC DEFINITION
Begin point: Rising edge of CK - CK# defined by the end point of ODTLCNW CK
Begin point: Rising edge of CK - CK# defined by the end point of ODTLCNW4 or ODTLCNW8
VCCQ/2 CK# t ADC t ADC
VRTT_NOM End point: Extrapolated point at VRTT_NOM
TSW21 TSW11 VSW1 VRTT_WR VSW2 TSW22 TSW12
VRTT_NOM
DQ, DM DQS, DQS#
End point: Extrapolated point at VRTT_WR VSSQ
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38
High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
ADVANCE INFORMATION
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
OUTPUT DRIVER IMPEDANCE FIGURE 19 - OUTPUT DRIVER
Chip in drive mode Output driver
34 OHM OUTPUT DRIVER IMPEDANCE
The 34 driver (MR1[5,1]=01) is the default driver. Unless otherwise stated, all timings and specifications listed herein apply to the 34 driver only. Its impedance RON is defined by the value of the external reference resistor RZQ as follows: RON34=RZQ/7 (with nominal RZQ=2401%) and is actually 34.31%. The 34 output driver impedance characteristics are listed in Table 35.
VCCQ IPU To other circuitry such as RCV, . . . RONPU DQ IOUT RONPD IPD VOUT VSSQ
TABLE 35: 34 DRIVER IMPEDANCE CHARACTERISTICS
MR1[5,1] RON RESISTOR
RON34PD 0, 1 34.3 RON34PU
PACKAGE OUTLINE DIMENSIONS
MIN
0.6 0.9 0.9 0.9 0.9 0.6 -10
VOUT
0.2/VccQ 0.5/VccQ 0.8/VccQ 0.2/VccQ 0.5/VccQ 0.8/VccQ
TYP
1.0 1.0 1.0 1.0 1.0 1.0 n/a
MAX
1.1 1.1 1.4 1.4 1.1 1.1 10
UNITS
RZQ/7 RZQ/7 RZQ/7 RZQ/7 RZQ/7 RZQ/7 %
NOTES
1 1 1 1 1 1 1, 2
Pull-Up/Pull-Down mismatch (MMPUPD) NOTES: 1.
0.5/VccQ
Tolerance limits assume RZQ of 240 (1%) and are applicable after proper ZQ calibration has been performed at a stable temperature and voltage (VccQ = Vcc, VssQ = Vss). Refer to "34 Ohm drive sensitivity" if either the temperature or the voltage changes after calibration
2.
Measurement definition for mismatch between pull-up and pull-down (MMPUPD). Mearure both RONPU and RONPD at 0.5 x VccQ: MMPUD = RONPU - RONPD RONNOM
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
ADVANCE INFORMATION
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
34 OHM OUTPUT DRIVER IMPEDANCE 34 OHM DRIVER
The 34 driver's current range has been calculated and summarized in Table 37 for Vcc=1.5V, Table 38 for Vcc=1.575V and Table 39 for Vcc=1.425V. The individual pull-up and pull-down resistors (RON34PD and RON34PU) are defined as follows with the Impedance Calculations listed in Table 36.
* RON34PD=(VOUT)/[IOUT]: RON34PU is turned off * RON34PU=(VccQ-VOUT)/[IOUT]: RON34PD is turned off
TABLE 36: 34 DRIVER PULL-UP AND PULL-DOWN IMPEDANCE CALCULATIONS DIMENSIONS PACKAGE OUTLINE
RON
RZQ = 2401% RZQ = (2401%)/7
MIN
237.6 33.9
TYP
240 34.3
MAX
242.4 34.6
UNITS

MR1[5,1]
RON
RESISTOR
RON34PD
VOUT
0.2/VccQ 0.5/VccQ 0.8/VccQ
MIN
2.04 30.5 30.5 30.5 30.5 20.4
TYP
34.3 34.3 34.3 34.3 34.3 34.3
MAX
38.1 38.1 48.5 48.5 38.1 38.1
UNITS

0, 1
34.3 RON34PU
0.2/VccQ 0.5/VccQ 0.8/VccQ
TABLE 37: 34 DRIVER IOH/IOL CHARACTERISTICS: VCC = VCCQ = 1.5V PACKAGE OUTLINE DIMENSIONS
MR1[5,1] RON RESISTOR
RON34PD 0, 1 34.3 RON34PU
VOUT
IOL @ 0.2 x VccQ IOL @ 0.5 x VccQ IOL @ 0.8 x VccQ IOL @ 0.2 x VccQ IOL @ 0.5 x VccQ IOL @ 0.8 x VccQ
MIN
14.7 24.6 39.3 39.3 24.6 14.7
TYP
8.8 21.9 35 35 21.9 8.8
MAX
7.9 19.7 24.8 24.8 19.7 7.9
UNITS
mA mA mA mA mA mA
TABLE 38: 34 DRIVER IOH/IOL CHARACTERISTICS: VCC=VCCQ=1.575V PACKAGE OUTLINE DIMENSIONS
MR1[5,1] RON RESISTOR
RON34PD 0, 1 34.3 RON34PU
VOUT
IOL @ 0.2 x VccQ IOL @ 0.5 x VccQ IOL @ 0.8 x VccQ IOL @ 0.2 x VccQ IOL @ 0.5 x VccQ IOL @ 0.8 x VccQ
MIN
15.5 25.8 41.2 41.2 25.8 15.5
TYP
9.2 23 36.8 36.8 23 9.2
MAX
8.3 20.7 26 26 20.7 8.3
UNITS
mA mA mA mA mA mA
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Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
34 OHM OUTPUT DRIVER IMPEDANCE TABLE 39: 34 DRIVER IOH/IOL CHARACTERISTICS: VCC=VCCQ=1.425V PACKAGE OUTLINE DIMENSIONS
MR1[5,1] RON RESISTOR
RON34PD 0, 1 34.3 RON34PU
VOUT
IOL @ 0.2 x VccQ IOL @ 0.5 x VccQ IOL @ 0.8 x VccQ IOL @ 0.2 x VccQ IOL @ 0.5 x VccQ IOL @ 0.8 x VccQ
MIN
14 23.3 37.3 37.3 23.3 14
TYP
8.3 20.8 33.3 33.3 20.8 8.3
MAX
7.5 18.7 23.5 23.5 18.7 7.5
UNITS
mA mA mA mA mA mA
34 OUTPUT DRIVER SENSITIVITY
If either the temperature or voltage changes after ZQ calibration, the tolerance limits listed in Table 35 can be expected to widen according to Table 40 and 41.
TABLE 40: 34 OUTPUT DRIVER SENSITIVITY DEFINITION
Symbol
RON @ 0.8 x VccQ RON @ 0.5 x VccQ RON @ 0.2 x VccQ
MIN
0.9 - dRONdTH x [T] + dRONdVH x [V] 0.9 - dRONdTM x [T] + dRONdVM x [V] 0.9 - dRONdTL x [T] + dRONdVL x [V]
MAX
1.1 - dRONdTH x [T] + dRONdVH x [V] 1.1 - dRONdTM x [T] + dRONdVM x [V] 1.1 - dRONdTL x [T] + dRONdVL x [V]
UNITS
RZQ/7 RZQ/7 RZQ/7
TABLE 41: 34 OUTPUT DRIVER VOLTAGE AND TEMPERATURE SENSITIVITY
Change
dRONdTM dRONdVM dRONdTL dRONdVL dRONdTH dRONdVH
MIN
0 0 0 0 0 0
MAX
1.5 0.13 1.5 0.13 1.5 0.13
UNITS
%/C %/mV %/C %/mV %/C %/mV
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
ALTERNATIVE 40 OHM DRIVER TABLE 42 - 40 DRIVER IMPEDANCE CHARACTERISTICS
MR1[5,1] RON RESISTOR
RON40PD 0, 1 40.0 RON40PU
PACKAGE OUTLINE DIMENSIONS
MIN
0.6 0.9 0.9 0.9 0.9 0.6 -10
VOUT
0.2/VccQ 0.5/VccQ 0.8/VccQ 0.2/VccQ 0.5/VccQ 0.8/VccQ
TYP
1.0 1.0 1.0 1.0 1.0 1.0 n/a
MAX
1.1 1.1 1.4 1.4 1.1 1.1 10
UNITS
RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/6 %
NOTES
1 1 1 1 1 1 1, 2
Pull-Up/Pull-Down mismatch (MMPUPD)
0.5/VccQ
NOTES: 1. Tolerance limits assume RZQ of 240 (1%) and are applicable after proper ZQ calibration has been performed at a stable temperature and voltage (VccQ = Vcc, VssQ = Vss). Refer to "40 Ohm drive sensitivity" if either the temperature or the voltage changes after calibration
2.
Measurement definition for mismatch between pull-up and pull-down (MMPUPD). Mearure both RONPU and RONPD at 0.5 x VccQ: MMPUPD = RONPU - RONPD RONNOM x 100
40 OUTPUT DRIVER SENSITIVITY
If either the temperature or voltage changes after I/O calibration, the tolerance limits listed in Table 42 can be expected to widen according to Table 43 and 44.
TABLE 43: 40 OUTPUT DRIVER SENSITIVITY DEFINITION
Symbol
RON @ 0.8 x VccQ RON @ 0.5 x VccQ RON @ 0.2 x VccQ
MIN
0.9 - dRONdTH x [T] + dRONdVH x [V] 0.9 - dRONdTM x [T] + dRONdVM x [V] 0.9 - dRONdTL x [T] + dRONdVL x [V]
MAX
1.1 - dRONdTH x [T] + dRONdVH x [V] 1.1 - dRONdTM x [T] + dRONdVM x [V] 1.1 - dRONdTL x [T] + dRONdVL x [V]
UNITS
RZQ/6 RZQ/6 RZQ/6
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42
High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
ALTERNATIVE 40 OHM DRIVER TABLE 44: 40 OUTPUT DRIVER VOLTAGE AND TEMPERATURE SENSITIVITY
Change
dRONdTM dRONdVM dRONdTL dRONdVL dRONdTH dRONdVH
MIN
0 0 0 0 0 0
MAX
1.5 0.15 1.5 0.15 1.5 0.15
UNITS
%/C %/mV %/C %/mV %/C %/mV
OUTPUT CHARACTERISTICS AND OPERATING CONDITIONS
The SDRAM uses both single-ended and differential output drivers. The single-ended output driver is summarized in Table 45 while the differential output driver is summarized in Table 46.
TABLE 45: SINGLE-ENDED OUTPUT DRIVER CHARACTERISTICS PACKAGE OUTLINE DIMENSIONS
Parameter/Condition
Output leakage current: DQ are disabled; 0V VOUT VccQ; ODT is disabled; ODT is HIGH Output slew rate: Single-ended; for rising and falling edges, measure between VOL(AC) = VREF - 0.1 x VccQ and VOH (AC) = VREF + 0.1 x VccQ Single-ended DC high-level output voltage Single-ended DC mid-point level output voltage Single-ended DC low-point level output voltage Single-ended DC high-point level output voltage Single-ended DC low-point level output voltage Delta RON between pull-up and pull-down for DQ/DQS Test load for AC timing and output slew rates NOTES: 1. RZQ of 240 (1%) with RZQ/7 enabled (default 34 driver) and is applicable after proper ZQ calibration has been performed at a stable temperature and voltage (VccQ = Vcc, VssQ = Vss). 2. 3. 4. VTT = VccQ/2 See Figure 31 on page 68 for the test load configuration. The 6V/ns maximum is applicable for a single DQ signal when it is switching from either HIGH to LOW or LOW to HIGH while the remaining DQ signals in the same byte lane are combinations, the maximum limit of 6V/ ns maximum is reduced to 5V/ns. 5. 6. 7. 8. See Table 35 on page 40 IV curve linearity. Do not use AC Test load. See Table 47 on page 47 for output slew rate. See Table 35 on page 40 for additional information. See Figure 29 on page 66 for an example of a single-ended output signal. VOH(DC) VOM(DC) VOL(DC) VOH(AC) VOL(AC) MMPUPD -10 Output to VTT (VccQ/2) via 25 resistor 0.8 x VccQ 0.5 x VccQ 0.2 x VccQ VTT + 0.1 x VccQ VTT - 0.1 x VccQ 10 V V V V V % 1, 2, 5 1, 2, 5 1, 2, 5 1, 2, 3, 6 1, 2, 3, 6 1, 7 3 SRQSE 2.5 6 V/ns 1, 2, 3, 4
Symbol
IOZ
MIN
-5
MAX
5
UNITS
uA
NOTES
1
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Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
TABLE 46: DIFFERENTIAL OUTPUT DRIVER CHARACTERISTICS PACKAGE OUTLINE DIMENSIONS
Parameter/Condition
Output leakage current: DQ are disabled; 0V VOUT VccQ; ODT is HIGH Output slew rate: Differential; for rising and falling edges, measure between VOLDIFF(AC) = - 0.2 x VccQ and VOH (AC) = + 0.2 x VccQ Output differential cross-point voltage Differential high-level output voltage Differential low-level output voltage Delta RON between pull-up and pull-down for DQ/DQS Test load for AC timing and output slew rates NOTES: 1. RZQ of 240 (1%) with RZQ/7 enabled (default 34 driver) and is applicable after proper ZQ calibration has been performed at a stable temperature and voltage (VccQ = Vcc, VssQ = Vss). 2. 3. VREF = VccQ/2 See Figure 31 on page 68 for the test load configuration. 4. 5. 6. See Table 48 on page 65 for the output slew rate. See Table 35 on page 58 for additional information. See Figure 30 on page 67 for an example of a differential output signal. VOX(AC) VOHDIFF(AC) VOLDIFF(AC) MMPUPD -10 VREF-150 + 0.2 x VccQ - 0.2 x VccQ 10 VREF+150 mV V V % 1, 2, 3 1, 4 1, 4 1, 5 3 SRQDIFF 5 12 V/ns 1
Symbol
IOZ
MIN
-5
MAX
5
UNITS
uA
NOTES
1
Output to VTT (VccQ/2) via 25 resistor
FIGURE 20 - DQ OUTPUT SIGNAL
MAX output
VOH(AC)
VOL(AC)
MIN output
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L9D320G32BG6
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OUTPUT CHARACTERISTICS AND OPERATING CONDITIONS FIGURE 21 - DIFFERENTIAL OUTPUT SIGNAL
MAX output
VOH(DIFF)
X
X
VOX(AC) MAX
X X VOX(AC) MIN
VOL(DIFF)
MIN output
REFERENCE OUTPUT LOAD
Figure 22 represents the effective reference load of 25 used in defining the relevant device AC timing parameters (except ODT reference timing) as well as the output slew rate measurements. It is not intended to be a precise representation of a particular system environment or a depiction of the actual load presented by any specific Industry test system/apparatus. System designers should use IBIS or other simulation tools to correlate the timing reference load presented or exhibited on the system or system environment.
FIGURE 22 - REFERENCE OUTPUT LOAD FOR AC TIMING AND OUTPUT SLEW RATE
VREF
VCCQ/2 RTT = 25
DUT
DQ DQS DQS# ZQ
VTT = VCCQ/2
Timing Reference Point RZQ = 240 VSS
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
SLEW RATE DEFINITIONS FOR SINGLE-ENDED OUTPUT SIGNALS
The single-ended output driver is summarized in Table 45. With the reference load for timing measurements, the output slew-rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single-ended signals as indicated in Table 47 and Figure 23.
TABLE 47: SINGLE-ENDED OUTPUT SLEW RATE
Output Slew Rate (Linear Signals) Output Edge
Rising DQ Falling VOH(AC)
PACKAGE OUTLINE DIMENSIONS
To
VOH(AC)
Measured From
VOL(AC)
Calculation
VOH(AC) - VOL (AC) TRSE
VOL(AC)
VOH(AC) - VOL(AC) TFSE
FIGURE 23 - NOMINAL SLEW RATE DEFINITION FOR SINGLE-ENDED OUTPUT SIGNALS
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High Performance, Integrated Memory Module Product
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
SLEW RATE DEFINITIONS FOR DIFFERENTIAL OUTPUT SIGNALS
The differential output driver is summarized in Table 46. With the reference load for timing measurements, the output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for differential signals, as shown in Table 48 and Figure 33.
TABLE 48: DIFFERENTIAL OUTPUT SLEW RATE DEFINITION
Output Slew Rate (Linear Signals) Output Edge
Rising DQS, DQS\ Falling VOHDIFF(AC)
PACKAGE OUTLINE DIMENSIONS
To Calculation
VOHDIFF(AC) - VOL DIFF(AC) TRDIFF
Measured From
VOLDIFF(AC)
VOHDIFF(AC)
VOLDIFF(AC)
VOHDIFF(AC) - VOLDIFF(AC) TFDIFF
FIGURE 24 - NOMINAL DIFFERENTIAL OUTPUT SLEW RATE DEFINITION FOR DQS, DQS#
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
TABLE 49: SPEED BINS PACKAGE OUTLINE DIMENSIONS
-25 (DDR3-800) [CWL=2.5; 6-6-6] -19 (DDR3-1066) [CWL=1.875; 8-8-8] -15 (DDR3-1333) [CWL=1.5; 10-10-10]
Parameter
ACTIVATE to internal READ or WRITE delay time PRECHARGE command period ACTIVATE-to-ACTIVATE or REFRESH command period ACTIVATE-to-PRECHARGE command period CWL=5 CL=5 CWL=6 CWL=7 CWL=5 CL=6 CWL=6 CWL=7 CWL=5 CL=8 CWL=6 CWL=7 CWL=5 CL=10 CWL=6 CWL=7 Supported CL Settings Supported CWL Settings
Symbol
tRCD tRP tRC tRAS tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG)
MIN
15 15 52.5 37.5 3
MAX
60ms 3.3
MIN
15 15 52.5 37.5 3
MAX
60ms 3.3
MIN
15 15 51 36 3
MAX UNITS NOTES
60ms 3.3 ns ns ns ns ns ns ns 1 2 3 3 2 3 3 3 2,3 3 3 3 2,3
2.5
3.3
2.5
3.3
2.5
3.3
ns ns ns ns
1.875
<2.5
1.875
<2
ns ns ns ns
1.5 5,6 5 5, 6, 8 5, 6
<1.875 5, 6, 7
ns CK CK
5, 6, 8, 10
NOTES: 1. 2. tREFI depends on tOPER The CL and CWL setting result in tCK requirements. When making a selection of tCK, both CL and CWL requirement settings need to be fulfilled. 3. Reserved (filled blocks) settings are not allowed.
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2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
High Performance, Integrated Memory Module Product
Symbol
t
ADVANCE INFORMATION
TABLE 50 (SHEET 1 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS
Parameter TC = 0C to <85C Clock period average: DLL TC = 85C to 105C disable mode TC = >105C to 125C Clock period average: DLL enable mode HIGH pulse width average LOW pulse width average CKDLL_DIS
t
-25 (DDR3-800) [CWL=2.5; 6-6-6] MIN MAX 8 7800 8 3900 8 2900 0.47 0.47 -100 -90 0.53 0.53 100 90
-19 (DDR3-1066) -15 (DDR3-1333) [CWL=1.875; 8-8-8] [CWL=1.5; 10-10-10] MIN MAX MIN MAX 8 7800 8 7800 8 3900 8 3900 8 2900 8 2900 0.47 0.47 -90 -80 0.53 0.53 90 80 0.47 0.47 -80 -70
Units
ns
Notes 9,42 9,42 9,42
CK (AVG)
t CH (AVG) t CL (AVG) t JITPER t JITPER, LCK t CLK (ABS) t
See SPEED BIN TABLE (#49) for tCK range allowed
Clock period JITTER Clock absolute period Clock absolute HIGH pusle width Clock absolute LOW pulse width Cycle-to-Cycle JITTER DLL LOCKED DLL LOCKING 2 Cycles 3 Cycles 4 Cycles 5 Cycles 6 Cycles 7 Cycles 8 Cycles 9 Cycles 10 Cycles 11 Cycles 12 Cycles n = 13, 14 ... 49, 50 Cycles
DLL LOCKED DLL LOCKING
0.53 0.53 80 70
MIN=tCK (AVG) MIN+tJITPER MIN; MAX=tCK (AVG)MAX+tJITPER MAX
ns CK CK ps ps ps CH (ABS)
t
10,11 12 12 13 13
0.43 CL (ABS)
t JITCC t JITCC, LCK ERR2PERR t t
0.43 200 180 -147 ERR3PERR
t ERR4PERR t ERR5PERR t ERR6PERR t ERR7PERR t ERR8PERR t ERR9PERR t ERR10PERR t ERR11PERR ERR12PERR
0.43 0.43 180 160 147 -175 -194 -209 -222 -232 -241 -249 -257 -263 -269
t t
-
0.43 0.43
-
tCK (AVG)
14
-
tCK (AVG)
15
160 140 -132 132 -118
118
ps ps ps
16 16 17
Cumula ve error across
ERRnPER
175 -157 157 -140 194 -175 175 -155 209 -188 188 -168 222 -200 200 -177 232 -209 209 -186 241 -217 217 -193 249 -224 224 -200 257 -231 231 -205 263 -237 237 -210 269 -242 242 -215 tERRnPER MIN = (1+0.68ln[n]) x tJITPER MIN tERRnPER MAX = (1+0.68ln[n]) x tJITPER MAX
ps
17
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140 155 168 177 186 193 200 205 210 215
ps ps ps ps ps ps ps ps ps ps
17 17 17 17 17 17 17 17 17 17
49
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
High Performance, Integrated Memory Module Product
-25 (DDR3-800) [CWL=2.5; 6-6-6] Symbol MIN MAX DQ Input Timing 75 t DS AC175 250 125 t DS AC150 275 150 t DH AC100 250 t 600 DIPW DQ Ouput Timing 200
t
ADVANCE INFORMATION
Parameter
-19 (DDR3-1066) -15 (DDR3-1333) [CWL=1.875; 8-8-8] [CWL=1.5; 10-10-10] MIN MAX MIN MAX 25 200 75 250 100 200 490 30 180 65 165 400
Units
Notes
TABLE 50 (SHEET 2 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS
Data SETUP me to DQS, DQS\ Data SETUP me to DQS, DQS\ Data HOLD me from DQS, DQS\ Minimum Data Pulse Width DQS, DQS\ to DQ SKEW, per access DQ Output HOLD me from DQS, DQS\ DQ LOW-Z me from CK, CK\ DQ HIGH-A me from CK, CK\ DQS,DQS\ RISING to CK, CK\ RISING DQS, DQS\ DIFFERENTIAL Input Low pulse width DQS, DQS\ DIFFERENTIAL Input HIGH pulse width DQS, DQS\ FALLING Setup to CK, CK\ RISING DQS, DQS\ FALLING Hold from CK, CK\ RISING DQS, DQS\ DIFFERENTIAL WRITE preamble DQS, DQS\ DIFFERENTIAL WRITE postamble DQS, DQS\ RISING to/from RISING CK, CK\ DQS, DQS\ RISING to/from RISING CK, CK\ when DLL is disabled DQS, DQS\ DIFFERENTIAL Output HIGH me DQS, DQS\ DIFFERENTIAL Output LOW me DQS, DQS\ LOW-Z me (RL-1) DQS, DQS\ HIGH-Z me (RL+BL/2) DQS, DQS\ DIFFERENTIAL READ preamble DQS, DQS\ DIFFERENTIAL READ postamble
Base (specifica on) VREF @ 1V/ns Base (specifica on) VREF @ 1V/ns Base (specifica on) VREF @ 1V/ns
DQSQ t
ps ps ps ps ps ps ps 150 QH
t LZ (DQ)
18,19 19,20 18,19 19,20 18,19 19,20 41 0.38 -800
t HZ (DQ) DQ Strobe Input Timing t -0.25 DQSS t 0.45 DQSL t 0.45 DQSH t 0.2 DSS t 0.2 DSH t 0.9 WPRE t 0.3 WPST DQ Strobe Output Timing -400 t DQSCK t DQSK DLL_DIS t QSH t QSL t LZ (DQS) t HZ (DQS) t RPRE
125 400 400 0.25 0.55 0.55 400 1 0.38 0.38 -800 0.9
t
ps 0.38 -600 -0.25 0.45 0.45 0.2 0.2 0.9 0.3 -300 10 400 400 Note 24 RPST 0.3 Note 27 1 0.38 0.38 -600 0.9 0.3 300 300 0.25 0.55 0.55 300 10 300 300 Note 24 Note 27 0.38 -500 -0.25 0.45 0.45 0.2 0.2 0.9 0.3 -255 1 0.4 0.4 -500 0.9 0.3
-
tCK (AVG)
21
250
ps
22,23
250
ps
22,23
0.25 0.55 0.55 -
CK CK CK CK CK CK CK
25
25 25
10
ns
26
250 250 Note 24
CK CK ps ps CK
21 21 22,23 22,23 23,24
LOGIC Devices Incorporated
Note 27
CK
23,27
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255
ps
23
50
Jul 08, 2009 LDS-L9D320G32BG6-A
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2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
High Performance, Integrated Memory Module Product
t RRD
ADVANCE INFORMATION
Parameter
TABLE 50 (SHEET 3 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS
DLL Locking me Base (specifica on) CTRL, CMD, ADDR setup to CK, VREF @ 1V/ns CK\ Base (specifica on) CTRL, CMD, ADDR setup to CK, VREF @ 1V/ns CK\ Base (specifica on) CTRL, CMD, ADDR hold to CK, VREF @ 1V/ns CK\ Minimum CTRL, CMD, ADDR pulse width ACTIVATE to Internal READ or WRITE delay PRECHARGE command period ACTIVATE-to-PRECHARGE command period ACTIVATE-to-ACTIVATE command period ACTIVATE-to-ACTIVATE minimum command period Four ACTIVATE windows for 1KB page size Four ACTIVATE windows for 2KB page size WRITE recovery me Delay from start of internal WRITE transac on to internal READ command READ-to-PRECHARE me CAS\-to-CAS\ command delay Auto precharge WRITE recovery + PRECHARGE me MODE REGISTER SET command cycle me MODE REGISTER SET command update delay MULTIPURPOSE REGISTER READ burst end to mode register set for mul purpose register exit
t
1KB page size 2KB page size
-25 (DDR3-800) -19 (DDR3-1066) -15 (DDR3-1333) [CWL=2.5; 6-6-6] [CWL=1.875; 8-8-8] [CWL=1.5; 10-10-10] Symbol MIN MAX MIN MAX MIN MAX Command and Address Timing t 512 512 512 DLLK 200 125 65 t IS AC175 375 300 240 350 275 190 t IS AC150 500 425 340 275 200 140 t IH DC100 375 300 240 t 900 780 620 IPW t See "Speed Bin Table (#49) for tRCD RCD t See "Speed Bin Table (#49) for tRP RP t See "Speed Bin Table (#49) for tRAS RAS t See "Speed Bin Table (#49) for tRC RCD MIN=greater of 4CK MIN=greater of 4CK MIN=greater of 4CK or 6ns or 10ns or 7.5ns MIN=greater of 4CK or 6ns MIN=greater of 4CK or 10ns
t
Units
Notes
CK ps ps ps ps ps ps ps ns ns ns ns
28 29,30 20,30 29,30 20,30 29,30 20,30 41 31 31 31,32 31
CK
31
CK FAW
t
31 40 50 WR WTR
t RTP t CCD t t t
-
37.5 50
MIN = 15ns; MAX = n/a
30 45
-
ns ns
31 31
CK
31,32,33
MIN = greater of 4CK or 7.5ns; MAX = n/a
CK
31,34
DAL MRD MOD
t
MIN = WR + tRP/tCK (AVG); MAX = n/a
CK
MIN = 4CK; MAX = n/a MIN = greater of 12CK or 15ns; MAX = n/a MPRR MIN = 1CK; MAX = n/a
CK CK
CK
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MIN = greater of 4CK or 7.5ns; MAX = n/a MIN = 4CK; MAX = n/a
CK CK
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
High Performance, Integrated Memory Module Product
-25 (DDR3-800) [CWL=2.5; 6-6-6] Symbol MIN MAX Calibra on Timing
t
ADVANCE INFORMATION
Parameter
-19 (DDR3-1066) -15 (DDR3-1333) [CWL=1.875; 8-8-8] [CWL=1.5; 10-10-10] MIN MAX MIN MAX 512 512 512
Units
Notes
TABLE 50 (SHEET 4 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS
ZQCL command: Long Calibra on me Normal opera on ZQCS command: Short Calibra on Time Exit RESET from CKE HIGH to a valid command Begin power supply ramp to power supplies stable RESET\ LOW to power supplies stable RESET\ LOW to I/O and RTT HIGH-Z
POWER-UP and RESET opera on
ZQINIT
-
CK
t 256 256 256 ZQOPER t 64 64 64 ZQCS Ini aliza on and RESET Timing MIN = greater of 5CK or tRFC + 10ns; MAX = n/a t XPR t
-
CK CK
CK VDDPR
t RPS t IOZ REFRESH Timing t
MIN = n/a; MAX = 200 MIN = 0; MAX = 200 MIN = n/a; MAX = 200 MIN = 110; MAX = 9 x tREFI RFC 64 32 24 7.8 3.9 2.9
ms
ms ns
35
Maximum REFRESH period Maximum REFRESH period/interval
TC 85C TC >85C 105C TC >105C 125C TC 85C TC >85C 105C TC >105C 125C
t REFI
ms ms ms s s s SELF REFRESH Timing
t
36 36 36 36 36 36 XS
t
Exit SELF REFRESH TO commands not requiring a locked DLL EXIT SELF REFRESH TO commands requiring a locked DLL MINIMUM CKE LOW pulse width for SELF REFRESH entry to SELF REFRESH exit ming Valid clocks a er SELF REFRESH entry or POWER-DOWN entry Valid clocks before SELF REFRESH exit, POWER-DOWN exit, or RESET exit
MIN = greater of 5CK or tRFC + 10ns; MAX = n/a XSDLL
t
CK MIN = tDLLK (MIN); MAX = n/a CKESR
t
CK MIN = tCKE (MIN) + CK; MAX = n/a CKSRE
t
28
CK
MIN = greater of 5CK or 10ns; MAX = n/a CKSRX
CK
MIN = greater of 5CK or 10ns; MAX = n/a
CK
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REFRESH-to-ACTIVATE or REFRESH command period
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High Performance, Integrated Memory Module Product
t CPDED t PD t
ADVANCE INFORMATION
TABLE 50 (SHEET 5 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS
Parameter CKE MIN pulse width Command pass disable delay POWER-DOWN entry to POWER-DOWN exit ming Begin POWER-DOWN period prior to CKE registered HIGH POWER-DOWN entry period: ODT e her synchronous or asynchronous POWER-DOWN exit period: ODT either synchronous or asynchronous ACTIVATE command to POWER-DOWN entry PRECHARGE/PRECHARGE ALL command to POWER-DOWN entry REFRESH command to POWER-DOWN entry MRS command to POWER-DOWN entry READ/READ with AUTO PRECHARGE commant to POWER-DOWN entry WRITE Command to POWERDOWN entry WRITE with AUTO PRECHARGE command to POWER-DOWN entry BL8 (OTF, MRS) BC4OTF BC4MRS BL8 (OTF, MRS) BC4OTF BC4MRS
t t
-25 (DDR3-800) -19 (DDR3-1066) -15 (DDR3-1333) [CWL=2.5; 6-6-6] [CWL=1.875; 8-8-8] [CWL=1.5; 10-10-10] Symbol MIN MAX MIN MAX MIN MAX POWER-DOWN Timing Greater of 3CK or Greater of 3CK or Greater of 3CK or t CKE (MIN) 7.5ns 5.625ns 5.625ns MIN = 1; MAX = n/a MIN = tCKE (MIN); MAX = 60ms ANPD PDE PDX POWER-DOWN Entry MINIMUM Timing ACTPDEN
t
Units
Notes
CK
CK CK WL - 1CK
CK
Greater of tANPD or tRFC - REFRESH command to CKE LOW me
t
CK ANPD + tXPDLL MIN = 1 PRPDEN
t REFPDEN t MRSPDEN t
CK
CK MIN = 1 MIN = 1 MIN = tMOD (MIN) RDPDEN
t t
CK
CK CK MIN = RL + 4 + 1 WRPDEN WRPDEN WRAPDEN
t WRAPDEN POWER-DOWN Exit Timing t
37
CK MIN = WL + 4 + tWR/tCK (AVG) MIN = WL + 2 + tWR/tCK (AVG) MIN = WL + 4 + WR + 1 MIN = WL + 2 + WR + 1
CK
CK
CK
CK MIN = Greater of 3CK or 7.5ns; MAX = n/a XP
t
DLL on, any valid command, or DLL off to commands not requiring DLL locked PRECHARGE POWER-DOWN with DLL off to command requiring DLL locked
MIN = Greater of 3CK or 6ns; MAX = n/a
CK XPDLL
MIN = Greater of 10CK or 24ns; MAX = n/a
CK
28
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
High Performance, Integrated Memory Module Product
-25 (DDR3-800) [CWL=2.5; 6-6-6] Symbol MIN MAX ODT Timing ODTL on ODTL off
t t t
ADVANCE INFORMATION
TABLE 50 (SHEET 6 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS
Parameter RTT synchronous TURN-ON delay RTT synchronous TURN-OFF delay RTT TURN-ON from ODTL ON reference RTT TURN-OFF from ODTL OFF reference Asynchronous RTT TURN-ON delay (POWER-DOWN with DLL OFF) Asynchronous RTT TURN-OFF delay (POWER-DOWN with DLL OFF) ODT HIGH me without WRITE command or with WRITE command and BC8 ODT HIGH me without WRITE command or with WRITE command and BC4 RTT_NOM-to=RTT_WR change skew RTT_WR-to-RTT_NOM change skew - BC4 RTT_WR-to-RTT_NOM change skew - BC8 RTT dynamic change skew First DQS, DQS\ RISING edge DQS; DQS\ delay WRITE Leveling SETUP from rising CK, CK\ crossing to rising DQS, DQS\ crossing WRITE Leveling HOLD from rising DQS, DQS\ crossing to rising CK, CK\ crossing WRITE Leveling output delay WRITE Leveling output error
-19 (DDR3-1066) -15 (DDR3-1333) [CWL=1.875; 8-8-8] [CWL=1.5; 10-10-10] MIN MAX MIN MAX
Units
Notes
AON AOF AONPD
t
-400 0.3
400 0.7
-300 0.3
300 0.7 MIN = 2; MAX = 8.5 AOFPD ODTH8 ODTH4 Dynamic ODT Timing ODTLCNW ODTLCNW4 ODTLCNW8 t 0.3 ADC WRITE Leveling Timing 40 25
t WLMRD t WLDQSEN t
-250 0.3
250 0.7
CK CK ps CK
38 40 23,38 39,40
ns MIN = 2; MAX = 8.5 MIN = 6; MAX = n/a MIN = 4; MAX = n/a WL - 2CK 4CK + ODTL OFF 6CK + ODTL OFF 0.3 0.7 0.7 WLS
t
38
ns
40
CK
0.3 40 25 325 WLH
t t WLO WLOE
0.7 325 0 0 9 2 245 245 0 0 9 2 40 25 195 195 0 0
CK CK CK CK
39
-
CK CK
-
ps
-
ps
9 2
ns ns
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CK
Jul 08, 2009 LDS-L9D320G32BG6-A
L9D320G32BG6
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
NOTES
1. 2. 3. 4. Parameters are applicable with 0C Tc +95C and Vcc/VccQ = + 1.5V 0.075V. All voltages are referenced to Vss. Output timings are only valid for RON34 output buffer selection. Unit tCK (AVG) represents the actual tCK (AVG) of the input clock under operation. Unit CK represents one clock cycle of the input clock, counting the actual clock edges. AC timing and ICC tests may use a VIL-to-VIH swing of up to 900mV I the test environment, but input timing is still referenced to VREF (except tIS, tIH, tDS, and tDH use the AC/DC trip points and CK, CK\ and DQS, DQS\ use their crossing points). The minimum slew rate for the input signals used to test the device is 1V/ns for single-ended inputs and 2V/ ns for differential inputs in the range between VIL (AC) and VIH (AC). All timings that use time-based values (ns, s, ms) should use tCK (AVG) to determine the correct number of clocks (Table 50 uses CK or CK (AVG) interchangeably). In the case of non-interger results, all minimum limits are to be rounded up to the nearest whole integer. The use of STROBE or DQSDIFF refers to the DQS and DQS\ differential crossing point when DQS is the rising edge. The use of CLOCK or CK refers to the CK and CK\ differential crossing point when CK is the rising edge. This output load is used for all AC timing (except ODT reference timing) and slew rates. The actual test load may be different. The output signal voltage reference point is VccQ/2 for single-ended signals and the crossing point for differential signals. When operating in DLL disable mode, LOGIC Devices, Inc. (LDI) does not warrant compliance with normal mode timings or functionality. 24. 10. The clock's tCK (AVG) is the average clock over any 200 consecutive clocks and tCK (AVG) MIN is the smallest clock rate allowed, with the exception of a deviation due to clock jitter. Input clock jitter is allowed provided it does not exceed values specified and must be of a random Gaussian distribution in nature. Spread spectrum is not included in the jitter specification values. However, the input clock can accommodate spread-spectrum at a sweep rate in the range of 20-60kHz with and additional 1% of tCK (AVG) as a long-term jitter component; however, the spread-spectrum may not use a clock rate below tCK (AVG) MIN. The clock's tCH (AVG) and tCL (AVG) are the average half clock period over any 200 consecutive clocks and is the smallest clock half period allowed, with the exception of values specified and must of a random Gaussian distribution in nature. The period jitter (tJITPER) is the maximum deviation in the clock period from the average or nominal clock. It is allowed in either the positive or negative direction.
tCH (ABS) is the absolute instantaneous clock high pulse width as measured from one rising edge to the following falling edge. tCL (ABS) is the absolute instantaneous clock low pulse width as measured from one falling edge to the following rising edge.
deviate from one cycle to the next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL locking time. 17. The cumulative jitter error (tERRnPER), where n is the number of clocks between 2 and 50, is the amount of clock time allowed to accumulate consecutively away from the average clock over n number of clock cycles.
tDS (base) and tDH (base) values are for a single-ended 1V/ns DQ slew rate and 2V/ns for differential DQS, DQS\ slew rate.
18.
5.
19.
These parameters are measured from a data signal (DM, DQ0, DQ1 ... DQn and so forth) transition edge to its respective data strobe signal (DQS, DQS\) crossing. The setup and hold times are listed converting the base specification values (to which derating tables apply) to VREF when the slew rate is 1V/ns. These values, with a slew rate of 1V/ns are for reference only. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJITPER (larger of tJITPER (MIN) or tJITPER (MAX) of the input clock (output deratings are relative to the SDRAM input clock). Single-ended signal parameter. The SDRAM output timing is aligned to the nominal or average clock. Most output parameters must be derated by the actual jitter error when input clock jitter is present, even when within specification. This results in each parameter becoming larger. The following parameters are required to be derated by subtracting tERR10PER (MAX); tDQSCK (MIN), tLZ (DQS) MAX, tLZ (DQ) MAX, and tAON (MAX). The parameter tRPRE (MIN) is derated by subtracting tJITPER (MAX), while tRPRE (MAX) is derated by tJITPER (MIN). The maximum preamble is bound by tLZDQS (MAX). These parameters are measured from a data strobe signal (DQS, DQS\) crossing to its respective clock signal (CK, CK\) crossing. The specification values are not affected by the amount of clock jitter applied, as these are relative to the clock signal crossing. These parameters should be met whether clock jitter is present or not. The tDQSCK DLL_DIS parameter begins CL + AL - 1 cycles after the READ command. The maximum postamble is bound by tHZDQS (MAX). Commands requiring a locked DLL are: READ (and RDAP) and synchronous ODT commands. In addition, after any change of latency tXPDLL, timing must be met.
tIS
20.
6.
21.
7.
22. 23.
8.
9.
25.
11.
26. 27. 28.
12.
29.
13.
(base) and tIH (base) values are for a single-ended 1 V/ns control/command/ address slew rate and 2 V/ns CK, CK# differential slew rate. These parameters are measured from a command/address signal transition edge to its respective clock (CK, CK\) signal crossing. The specification values are not affected by the amount of clock jitter applied as the setup and hold times are relative to the clock signal crossing that latches the command/address. These parameters should be met whether clock jitter is present or not. For these parameters, the DDR3 SDRAM device supports tnPARAM (nCK) = RU (tPARAM [ns]/ tCK[AVG][ns]), assuming all input clock
30.
14.
15.
31.
16.
The cycle-to-cycle jitter (tJITCC) is the amount the clock period can
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NOTES CONTINUED
jitter specifications are satisfied. For example, the device will support tnRP (nCK) = RU (tRP)/tCK[AVG]) if all input clock jitter specifications are met. This means for DDR2-800; 6-6-6, of which tRP = 15ns, the device will support tnRP = RU (tRP/tCK [AVG]) = 6 as long as the input clock jitter specifications are met. That is, the PRECHARGE command at T0 and the ACTIVATE command at T0+6 are valid even if six clocks are less than 15ns due to input clock jitter. 32. During READs and WRITEs with AUTO PRECHARGE, the DDR3 SDRAM will hold off the internal PRECHARGE command until tRAS (MIN) has been satisfied. When operating in DLL disable mode, the greater of 4CK or 15ns is satisfied for tWR. The start of the write recovery time is defined as follows: * For BL8 (fixed by MRS and OTF): Rising clock edge four clock cycles after WL. * For BC4 (OTF): Rising clock edge four clock cycles after WL. * For BC4 (fixed by MRS): Rising clock edge two clock cycles after WL. 35. RESET\ should be LOW as soon as power starts to ramp to ensure the outputs are in HIGH-Z Until RESET\ is LOW, the outputs are at risk of driving the bus and could result in excessive current, depending on the bus activity. The refresh period is 64ms when Tc is less than or equal to 85C. This equates to an average refresh rate of 7.8124s. However, nine REFRESH commands should be asserted at least once every 70.3s. When Tc is greater than 85C, the refresh period is 32ms and when Tc is greater than 105C, the refresh period is 24ms. 41. 42. 40. 37. Although CKE is allowed to be registered LOW after a REFRESH command when tREFPDEN (MIN) is satisfied, there are cases where additional time such as tXPDLL (MIN) is required. ODT turn-on time MIN is when the device leaves HIGH-Z and ODT resistance begins to turn on. ODT turn-on time maximum is when the ODT resistance is fully on. The ODT reference load is shown in Figure 23. Half-clock output parameters must derated by the actual tERR10PER and tJITDTY when input clock jitter is present. This results in each parameter becoming larger. The parameters tADC (MIN) and tAOF(MIN) are each required to be derated by subtracting both tERR10PER (MAX) and tJITDTY (MAX). The parameters tADC (MAX) and tAOF (MAX) are required to be derated by subtracting both tERR10PER (MAX) and tJITDTY (MAX). ODT turn-off time minimum is when the device starts to turn off ODT resistance. ODT turn-off time maximum is when the SDRAM buffer is in HIGH-Z. The ODT reference load is shown in Figure 24. This output load is used for ODT timings (see Figure 31). Pulse width of an input signal is defined as the width between the first crossing of VREF (DC) and the consecutive crossing of VREF(DC). Should the clock rate be larger than tRFC(MIN), an AUTO REFRESH command should have at least one NOP command between it and another AUTO REFRESH command. Additionally, if the clock rate is slower than 40ns (25MHz) all REFRESH commands should be followed by a PRECHARGE ALL command.
38.
39.
33. 34.
36.
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COMMAND AND ADDRESS SETUP, HOLD, AND DERATING
The total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH (base) values (Tables 51) to the tIS and tIH derating values (Table 52), respectively.
Although the total setup time for slow slew rates might be negative, a valid input signal is still required to complete the transition and to reach VIH(AC)/VIL(AC) (see Figure 14 for input signal requirements). For slew rates which fall between the values listed in Table 52 and Table 53, the derating values may be obtained by linear interpolation.
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC) MIN. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC) MAX. If the actual signal is always earlier than the nominal slew rate line between the shaded "VREF(DC)-to-AC region", use the nominal slew rate for derating value (see Figure 25). If the actual signal is later than the nominal slew rate line anywhere between the shaded "VREF(DC)-to-AC region", the slew rate of a tangent line to the actual signal from the AC level to the DC level is used for the derating value (see Figure 27).
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC) MAX and the first crossing of VREF(DC). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC) MIN and the first crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line between the shaded "DC-to-VREF(DC) region", use the nominal slew rate for derating value (see Figure 26). If the actual signal is earlier than the nominal slew rate line anywhere between the shaded "DC-to-VREF(DC) region", the slew rate of a tangent line to the actual signal from the DC level to the VREF(DC) level is used for the derating value (see Figure 28).
TABLE 51: COMMAND AND ADDRESS SETUP AND HOLD VALUES REFERENCED AT 1V/NS - AC/DC BASED
Symbol
tIS(base)AC175 tIS(base)AC150 tIH(base)DC100
DDR3-800
200 350 275
DDR3-1066
125 275 200
DDR3-1333
65 190 140
UNITS
ps ps ps
REFERENCE
VIH(AC)/VIL(AC) VIH(AC)/VIL(AC) VIH(AC)/VIL(AC)
TABLE 52: DERATING VALUES FOR tIS/tIH - AC175/DC100-BASED
Shaded cells indicate slew-rate combinations not supported
tIS, tIH Derating (ps) - AC/DC-Based, AC175 Threshold; VIH(AC) = VREF(DC) + 175mV, VIL(AC) = VREF(DC) - 175mV CMD/ADDR Slew Rate V/ns
2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4
CK, CK\ Differential Slew Rate
4.0V/ns 3.0V/ns 2.0V/ns 1.8V/ns 1.6V/ns 1.4V/ns 1.2V/ns 1.0V/ns
tIS
88 59 0 -2 -6 -11 -17 -35 -62
tIH
50 34 0 -4 -10 -16 -26 -40 -60
tIS
88 50 0 -2 -6 -11 -17 -35 -62
tIH
50 34 0 -4 -10 -16 -26 -40 -60
tIS
88 59 0 -2 -6 -11 -17 -35 -62
tIH
50 34 0 -4 -10 -16 -26 -40 -60
tIS
96 67 8 6 2 -3 -9 -27 -54
tIH
58 42 8 4 -2 -8 -18 -32 -52
tIS
96 67 8 6 2 -3 -9 -27 -54
tIH
66 50 16 12 6 0 -10 -24 -44
tIS
112 83 24 22 18 13 7 -11 -38
tIH
74 58 24 20 14 8 -2 -16 -36
tIS
120 91 32 30 26 21 15 -2 -30
tIH
84 68 34 30 24 18 8 -6 -26
tIS
128 99 40 38 34 29 23 5 -22
tIH
100 84 50 46 40 34 24 10 -10
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TABLE 53: DERATING VALUES FOR tIS/tIH - AC150/DC100-BASED
Shaded cells indicate slew-rate combinations not supported
tIS, tIH Derating (ps) - AC/DC-Based, AC150 Threshold; VIH(AC) = VREF(DC) + 150mV, VIL(AC) = VREF(DC) - 150mV CMD/ADDR Slew Rate V/ns
2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4
CK, CK\ Differential Slew Rate
4.0V/ns 3.0V/ns 2.0V/ns 1.8V/ns 1.6V/ns 1.4V/ns 1.2V/ns 1.0V/ns
tIS
75 50 0 0 0 0 -1 -10 -25
tIH
50 34 0 -4 -10 -16 -26 -40 -60
tIS
75 50 0 0 0 0 -1 -10 -25
tIH
50 34 0 -4 -10 -16 -26 -40 -60
tIS
75 50 0 0 0 0 -1 -10 -25
tIH
50 34 0 -4 -10 -16 -26 -40 -60
tIS
83 58 8 8 8 8 7 -2 -17
tIH
58 42 8 4 -2 -8 -18 -32 -52
tIS
91 66 16 16 16 16 15 6 -9
tIH
66 50 16 12 6 0 -10 -24 -44
tIS
99 74 24 24 24 24 23 14 -1
tIH
74 58 24 20 14 8 -2 -16 -36
tIS
107 82 32 32 32 32 31 22 7
tIH
84 68 34 30 24 18 8 -6 -26
tIS
115 90 40 40 40 40 39 30 15
tIH
100 84 50 46 40 34 24 10 -10
TABLE 54: MINIMUM REQUIRED TIME tVAC ABOVE VIH(AC) FOR A VALID TRANSITION
Below VIL(AC)
Slew Rate (V/ns)
>2.0 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 <0.5
tVAC
at 175mV(ps)
75 57 50 38 34 29 22 13 0 0
tVAC
at 150mV(ps)
175 170 167 163 162 161 159 155 150 150
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FIGURE 25 - NOMINAL SLEW RATE AND tVAC FOR tIS (COMMAND AND ADDRESS - CLOCK)
t IS CK
t IH
t IS
t IH
CK# DQS#
DQS
VCCQ t VAC
VIH(AC) MIN VREF to AC region VIH(DC) MIN Nominal slew rate VREF(DC) Nominal slew rate VIL(DC) MAX VREF to AC region VIL(DC) MAX
t VAC
VSS
TF VREF(DC) - VIL(AC) MAX = TF
TR VIH(AC) MIN - V REF(DC) = TR
Setup slew rate falling signal
Setup slew rate risin g signal
Notes:
1. Both the clock and the strobe are drawn on different time scales.
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FIGURE 26 - NOMINAL SLEW RATE FOR tIH (COMMAND AND ADDRESS - CLOCK)
t IS CK
t IH
t IS
t IH
CK# DQS#
DQS
VCCQ
VIH(AC) MIN
VIH(DC) MIN
DC to VREF region VREF(DC) Nominal slew rate
Nominal slew rate
DC to VREF region
VIL(DC) MAX
VIL(AC) MAX
VSS
TR Hol d slew rate = rising signal VREF(DC) - VIL(DC) MAX TR
TF VIH(DC) MIN - V REF(DC) TF
Hol d slew rate falling signal =
Notes:
1. Both the clock and the strobe are drawn on different time scales.
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FIGURE 27 - TANGENT LINE FOR tIS (COMMAND AND ADDRESS - CLOCK)
t IS CK t IH t IS t IH
CK# DQS#
DQS
VCCQ Nominal line VIH(AC) MIN VREF to AC region VIH(DC) MIN Tangent line t VAC
VREF(DC) Tangent line
VIL(DC) MAX VREF to AC region VIL(AC) MAX Nominal line VSS Setup slew rate rising signal = Tangent line (VIH [DC] MIN - VREF[DC ]) TR
t VAC
TR
TF
Tangent line (VREF [DC] - VIL[AC] MAX) Setup slew rate falling signal = TF
Notes:
1. Both the clock and the strobe are drawn on different time scales.
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FIGURE 28 - TANGENT LINE FOR tIH (COMMAND AND ADDRESS - CLOCK)
t IS CK t IH t IS t IH
CK# DQS #
DQS
VCCQ
VIH(AC) MIN Nominal line VIH(DC) MIN DC to VREF region
Tangent line
VREF(DC) DC to VREF region VIL( DC) MAX Tangent line Nominal line
VIL( AC) MAX
VSS
TR Hol d slew rate rising signal = Hol d slew rate falling signal = Tangent line (VREF [DC] - VIL[DC] MAX) TR Tangent line (VIH [DC] MIN - VREF[DC]) TF
TR
Notes:
1. Both the clock and the strobe are drawn on different time scales.
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DATA SETUP, HOLD AND DERATING
The total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS (base) and tDH (base) values (see Table 55) to the tDS and tDH derating values (see Table 56), respectively. Although the total setup time for slow slew rates might be negative, a valid input signal is still required to complete the transition and to reach VIH/VIL(AC). For slew rates which fall between the values listed in Table 57, the derating values may be obtained by linear interpolation. Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC) MIN. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC) MAX. If the actual signal is always earlier than the nominal slew rate line between the shaded "VREF(DC)-to-AC region", use the nominal slew rate derating value (see Figure 29). If the actual signal is later than the nominal slew rate line anywhere between the shaded "VREF(DC)-to-AC region", the slew rate of a tangent line to the actual signal from the AC level to the DC level is used for the derating value (see Figure 31). Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC) MAX and the first crossing of VREF(DC). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC) MIN and the first crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line between the shaded "DC-to-VREF(DC) region", use the nominal slew rate for derating value (see Figure 30). If the actual signal is earlier than the nominal slew rate line anywhere between the shaded "DC-to-VREF(DC) region", the slew rate of a tangent line to the actual signal from the "DC-to-VREF(DC) region", is used for the derating value (see Figure 32).
TABLE 55: DATA SETUP AND HOLD VALUES AT 1V/NS (DQSX, DQSX\ AT 2V/NS) - AC/DC BASED
Symbol
tDS(base)AC175 tDS(base)AC150 tDS(base)DC100
DDR3-800
75 125 150
DDR3-1066
25 75 100
DDR3-1333
30 65
UNITS
ps ps ps
REFERENCE
VIH(AC)/VIL(AC) VIH(AC)/VIL(AC) VIH(AC)/VIL(AC)
TABLE 56: DERATING VALUE FOR tDS/tDH - AC175/DC100 - BASED
Shaded cells indicate slew-rate combinations not supported
tDS, tDH Derating (ps) - AC175/D100-Based DQ Slew Rate V/ns
2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4
DQS, DQS# Differential Slew Rate
4.0V/ns 3.0V/ns 2.0V/ns 1.8V/ns 1.6V/ns 1.4V/ns 1.2V/ns 1.0V/ns
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
88 59 0 50 34 0 88 59 0 -2 50 34 0 -4 88 59 0 -2 -6 50 34 0 -4 -10 67 8 6 2 -3 42 8 4 -2 -8 16 14 10 5 -1 16 12 6 0 -10 22 18 13 7 -11 20 14 8 -2 -16 26 21 15 -2 -30 24 18 8 -6 -26 29 23 5 -22 34 24 10 -10
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TABLE 57: DERATING VALUE FOR tDS/tDH - AC150/DC100 - BASED
Shaded cells indicate slew-rate combinations not supported
tDS, tDH Derating (ps) - AC150/DC100-Based DQ Slew Rate V/ns
2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4
DQS, DQS# Differential Slew Rate
4.0V/ns 3.0V/ns 2.0V/ns 1.8V/ns 1.6V/ns 1.4V/ns 1.2V/ns 1.0V/ns
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
75 50 0 50 34 0 75 50 0 0 50 34 0 -4 75 50 0 0 0 50 34 0 -4 -10 58 8 8 8 8 42 8 4 -2 -8 16 16 16 16 15 16 12 6 0 -10 24 24 24 23 14 20 14 8 -2 -16 32 32 31 22 7 24 18 8 -6 -26 40 39 30 15 34 24 10 -10
TABLE 58: REQUIRED TIME tVAC ABOVE VIH(AC) (BELOW VIL[AC]) FOR A VALID TRANSITION
Slew Rate (V/ns)
>2.0 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 <0.5
tVAC
at 175mV(ps) [MIN]
75 57 50 38 34 29 22 13 0 0
tVAC
at 150mV(ps) [MIN]
175 170 167 163 162 161 159 155 150 150
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FIGURE 29 - NOMINAL SLEW RATE AND tVAC FOR tDS (DQ - STROBE)
CK
CK# DQS#
DQS t DS VCCQ t VAC t DH t DS t DH
VIH(AC) MIN VREF to AC region VIH(DC) MIN Nominal slew rate VREF(DC) Nominal slew rate VIL(DC) MAX VREF to AC region VIL(AC) MAX
t VAC VSS
TF Setup slew rate = rising signal VREF(DC) - VIL(AC) MAX TF
TR VIH(AC) MIN - VREF (DC) TR
Setup slew rate = rising signal
Notes:
1. Both the clock and the strobe are drawn on different time scales.
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FIGURE 30 - NOMINAL SLEW RATE FOR tDH (DQ - STROBE)
CK
CK# DQS#
DQS t DS t DH t DS t DH
VCCQ
VIH(AC) MIN
VIH(DC) MIN DC to VREF region Nominal slew rate
VREF(DC) Nominal slew rate
DC to VREF region
VIL(DC) MAX
VIL(AC) MAX
VSS
TR VREF(DC) - VIL(DC) MAX TR
TF VIH(DC) MIN - V REF(DC) TF
Hold slew rate = rising signal
Hold slew rate = falling signal
Notes:
1. Both the clock and the strobe are drawn on different time scales.
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FIGURE 31 - NOMINAL SLEW RATE AND tVAC FOR tDS (DQ - STROBE)
CK
CK# DQS#
DQS t DS VCCQ Nominal line t VAC t DH t DS t DH
VIH(AC) MIN VREF to AC region VIH(DC) MIN Tangent line
VREF(DC) Tangent line
VIL(DC) MAX VREF to AC region VIL(AC) MAX Nominal line t VAC VSS Setup slew rate rising signal Tangent line (V IH[AC] MIN - VREF [DC]) TR TF Setup slew rate falling signal Tangent line (VREF[DC] - VIL[AC] MAX) TF TR
=
=
Notes:
1. Both the clock and the strobe are drawn on different time scales.
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FIGURE 32 - NOMINAL SLEW RATE FOR tDH (DQ - STROBE)
CK
CK# DQS#
DQS t DS VCCQ t DH t DS t DH
VIH(AC) MIN Nominal line VIH(DC) MIN DC to VREF region
Tangent line
VREF(DC) Tangent line Nominal line
DC to VREF region VIL(DC) MAX
VIL(AC) MAX
VSS
TR Tangent line (VREF[DC] - VIL[DC] MAX) = TR Tangent line (VIH [DC] MIN - VREF[DC]) = TF
TF
Hol d slew rate falling signal
Hol d slew rate falling signal
Notes:
1. Both the clock and the strobe are drawn on different time scales.
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
COMMANDS TRUTH TABLE TABLE 59: TRUTH TABLE - COMMAND
CKE Function
Mode Register Set REFRESH SELF REFRESH entry SELF REFRESH exit
Single-Bank PRECHARGE
PACKAGE OUTLINE DIMENSIONS
CS\
L L L
H L
Symbol
MRS REF SRE SRX PRE PREA ACT
BL8MRS BC4MRS
Prev Cycle
H H H L H H H H H H H H H H H H H H H H H H L H H
Next Cycle
H H L H H H H H H H H H H H H H H H H H H L H H H
RAS\
L L L
V H
CAS\
L L L
V H
WE\
L H H
V H
BA[2:0]
BA V V V VBA V BA BA BA BA BA BA BA BA BA BA BA BA BA V X V V X X
An
V V V V V
A12
V V V V V
A10
V V V L H
A[11,0:0] Notes
V V V V V CA 6 6,7
L L L L L L L L L L L L L L L L H
L H L H
L L L H H H H H H H H H H H H H X
H V H V
L L L H H H H H H H H H H H H H X
H V H V
L L H L L L L L L H H H H H H H X
H V H V
PRECHARGE all banks Bank ACTIVATE
WR WRS4 WRS8 WRAP WRAPS4 WRAPS8 RD RDS4 RDS8 RDAP RDAPS4 RDAPS8 NOP DES PDE PDX ZQCL ZQCS
RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU V X V V X X
V L H V L H V L H V L H V X V V X X
L L L H H H L L L H H H V X V V H L
CA CA CA CA CA CA CA CA CA CA CA CA V X V V X X
8 8 8 8 8 8 8 8 8 8 8 8 9 10 6 6,11 12
WRITE
BC4OTF BL8OTF BL8MRS BC4MRS BC4OTF BL8OTF BL8MRS BC4MRS
WRITE with AUTO
PRECHARGE
READ
BC4OTF BL8OTF
READ with AUTO
PRECHARGE
BL8MRS BC4MRS BC4OTF BL8OTF
NO OPERATION Device DESELECTED POWER-DOWN entry POWER-DOWN exit ZQ CALIBRATION LONG ZQ CALIBRATION SHORT
L L
H H
H H
L L
NOTES: 1. Commands are defined by states of CS\, RAS\, CAS\, WE\, and CKE at the rising edge of the clock. The MSB of BA, RA, and CA are devicedensity and configuration-dependent. 2. 3. 4. 5. 6. 7. RESET\ is LOW enabled and used only for asynchronous RESET. Thus, RESET\ must be held HIGH during any normal operation. The state of ODT does not affect the states described in this table. Operations apply to the bank defined by the bank address. For MRS, BA selects one of four mode registers. "V" means "H" or "L" (a defined logic level), and "X" means "Don't Care". See Table 59 for additional information on CKE transition. SELF REFRESH exit is asynchronous.
8. 9.
Burst READs or WRITEs cannot be terminated or interrupted, MRS (fixed) and OTF BL/BC are defined in MR0. The purpose of the NOP command is to prevent the SDRAM from registering any unwanted commands. A NOP will not terminate and operation that is in execution.
10. 11. 12.
The DES and NOP commands perform similarly. The POWER-DOWN mode does not perform any REFRESH operations. ZQ CALIBRATION LONG is used for either ZQINT (first ZQCL command during initialization) or ZQOPER (ZQCL command after initialization).
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Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
TABLE 60: TRUTH TABLE - CKE
CKE (n-1) (n)
Current State 3
POWER-DOWN
Previous Cycle 4
L L
Present Cycle 4
L H L H L L L L L L
(RAS\, CAS\, WE\, CS\) Command 5
Action 5
Maintain POWER-DOWN POWER-DOWN exit Maintain SELF REFRESH SELF REFRESH exit Active POWER-DOWN entry POWER-DOWN entry POWER-DOWN entry PRECHARGE POWER-DOWN entry PRECHARGE POWER-DOWN entry SELF REFRESH
Notes
1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2,6
"Don't Care" DES or NOP "Don't Care" DES or NOP DES or NOP DES or NOP DES or NOP DES or NOP DES or NOP REFRESH
SELF REFRESH Bank(s) ACTIVE READING WRITING PRECHARGING REFRESHING All Banks IDLE
L H H H H H H H
NOTES: 1.
2.
All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
tCKE(MIN)
4. 5.
CKE (n) is the logic state of CKE at clock edge n, CKE (n-1) was the state of CKE at the previous clock edge. COMMAND is the command registered at the clock edge (must be a legal command as defined in Table 58). Action is a result of COMMAND. ODT does not affect the states described in this table and is not listed.
means CKE must be registered at multiple consecutive posi-
tive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the required number of registration clocks. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + tCKE(MIN) + tIH. 3. Current state = The state of the SDRAM immediately prior to clock edge n. 6.
Idle state = all banks are closed, no data bursts are in progress, CKE is HIGH and all timings from previous operations are satisfied. All SELF REFRESH exit and POWER-DOWN exit parameters are also satisfied.
DESELECT (DES)
The DES command (CS\ HIGH) prevents new commands from being executed by the SDRAM. Operations already in progress are not affected.
NO OPERATION (NOP)
The NOP command (CS\ LOW) prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected.
ZQ CALIBRATION
ZQ Calibration LONG (ZQCL)
The ZQCL command is used to perform the initial calibration during a power-up initialization and reset sequence. This command may be issued at any time by the controller depending on the system environment. The ZQCL command triggers the calibration engine inside the SDRAM. After calibration is achieved, the calibrated values are transferred from the calibration engine to the SDRAM I/O, which are reflected as updated RON and ODT values. The SDRAM is allowed a timing window defined by either tZQINIT or tZQOPER to perform the full calibration and transfer of values. When ZQCL is issued during the initialization sequence, the timing parameter tZQINIT must be satisfied. When initialization is complete, subsequent ZQCL commands require the timing parameter tZQOPER to be satisfied.
ZQ Calibration SHORT (ZQCS)
The ZQCS command is used to perform periodic calibrations to account for small voltage and temperature variations. The shorter timing window is provided to perform the reduced calibration and transfer of values as defined by timing parameter tZQCS. A ZQCS command can effectively correct a minimum of 0.5% RON and RTT impedance errors within 64 clock cycles, assuming the maximum sensitivities specified in Table 40 and Table 41.
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
ACTIVATE
The ACTIVATE command is used to open (or ACTIVATE) a row in a particular bank for a subsequent access. The value on the BA [2:0] inputs selects the bank, and the address provided on inputs A[n:0] selects the row. This row remains open (or ACTIVE) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank.
READ
The READ command is used to initiate a burst READ access to an ACTIVE row. The address provided on inputs A[2:0] selects the starting column address depending on the burst length and burst type selected (see table 65). The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be PRECHARGED at the end of the READ burst. If AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses. The value on input A12 (if enabled in the MODE REGISTER) when the READ command is issued, determines whether BC4 (chop) or BL8 is used. After a READ command is issued, the READ burst may not be interrupted. A summary of READ commands is shown in Table 61.
TABLE 61: READ COMMAND SUMMARY
CKE Function
BL8MRS BC4MRS
Symbol
RD RDS4 RDS8 RDAP RDAPS4 RDAPS8
Prev Cycle
H H H H H H
Next Cycle
CS\
L L L L L L
RAS\
H H H H H H
CAS\
L L L L L L
WE\
H H H H H H
BA[2:0]
BA BA BA BA BA BA
An
RFU RFU RFU RFU RFU RFU
A12
V L H V L H
A10
L L L H H H
A[11,0:0] Notes
CA CA CA CA CA CA
READ
BC4OTF BL8OTF BL8MRS BC4MRS BC4OTF BL8OTF
READ with AUTO
PRECHARGE
WRITE
The WRITE command is used to initiate a burst WRITE access to an ACTIVE row. The value on the BA[2:0] inputs selects the bank. The value on input A10 determines whether or not AUTO PRECHARGE is used. The value on input A12 (if enabled in the MODE REGISTER [MR]) when the WRITE command is issued, determines whether BC4 (chop) or BL8 is used. The WRITE command summary is shown in Table 62.
TABLE 62: WRITE COMMAND SUMMARY
CKE Function
BL8MRS BC4MRS
Symbol
WR WRS4 WRS8 WRAP WRAPS4 WRAPS8
Prev Cycle
H H H H H H
Next Cycle
CS\
L L L L L L
RAS\
H H H H H H
CAS\
L L L L L L
WE\
L L L L L L
BA[2:0]
BA BA BA BA BA BA
An
RFU RFU RFU RFU RFU RFU
A12
V L H V L H
A10
L L L H H H
A[11,0:0] Notes
CA CA CA CA CA CA
WRITE
BC4OTF BL8OTF BL8MRS BC4MRS BC4OTF BL8OTF
WRITE with AUTO
PRECHARGE
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
PRECHARGE
The PRECHARGE command is used to DEACTIVATE the open row in a particular bank or in all banks. The bank(s) are available for a subsequent row access at a specified time (tRP) after the PRECHARGE command is issued, except in the case of concurrent AUTO PRECHARGE. A READ or WRITE command to a different bank is allowed during concurrent AUTO PRECHARGE as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. Input A10 determines whether one or all banks are precharged. In the case where only one bank is recharged. Inputs BA[2:0] select the bank; otherwise, BA[2:0] are treated as "Don't Care". After a bank is PRECHARGED, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command is treated as a NOP if there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging. However, the PRECHARGE period is determined by the last PRECHARGE command issued to the bank.
REFRESH
REFRESH is used during normal operation of the SDRAM and is analogous to CAS\-before RAS\ (CBR) refresh or AUTO REFRESH. This command is non-persistent, so it must be issued each time a REFRESH is required. The addressing is generated by the internal REFRESH command. The SDRAM requires REFRESH cycles at an average interval of 7.8s (maximum when Tc85C or 3.9s MAX when Tc95C). The REFRESH period begins when the REFRESH command is registered and ends tRFC (MIN) later. To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute REFRESH interval is provided. A maximum of eight REFRESH commands can be posted to any given SDRAM, meaning that the maximum absolute interval between any REFRESH command and the next REFRESH command is nine times the maximum average interval refresh rate. SELF REFRESH may be entered with up to eight REFRESH commands being posted. After exiting SELF REFRESH (when entered with posted REFRESH commands) additional posting of REFRESH commands is allowed to the extent the maximum number of cumulative posted REFRESH commands (both pre and post SELF REFRESH) does not exceed eight REFRESH commands.
FIGURE 33 - REFRESH MODE
T0 CK# CK
T1
T2
T3
T4
Ta0
Ta1
Tb0
Tb1
Tb2
t CK
t CH
t CL Valid 1 Valid 1 Valid 1
CKE
Command
NOP 1
PRE
NOP 1
NOP 1
REF
NOP 1
REF 2
NOP1
NOP1
ACT
Address All banks A10 One bank
RA
RA
BA[2:0]
Bank(s) 3
BA
DQS, DQS# 4
DQ4
DM 4 t RP t RFC (MIN) t RFC 2
Indicates A Break in Time Scale
Don't Care
Notes:
1. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. CKE must be active during the PRECHARGE, ACTIVATE, and REFRESH commands, but may be inactive at other times (see "Power-Down Mode" on page 153).
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
SELF REFRESH
The SELF REFRESH command is used to retain data in the SDRAM, even if the rest of the system is powered down. When in the SELF REFRESH mode, the SDRAM retains data without external clocking. The SELF REFRESH mode is also a convenient method used to enable/disable the DLL as well as to change the clock frequency within the allowed synchronous operating range. All power supply inputs (including VREFCA and VREFDQ) must be maintained at valid levels upon entry/exit and during SELF REFRESH mode operation. All power supply inputs (including VREFCA and VREFDQ) must be maintained at valid levels upon entry/exit and during SELF REFRESH mode under certain conditions: * Vss< VREFDQ< Vcc is maintained * VREFDQ is valid and stable prior to CKE going back HIGH * The first WRITE operation may not occur earlier than 512 clocks after VREFDQ is valid * All other SELF REFRESH mode exit time requirements are met.
DLL DISABLE MODE
If the DLL is disabled by the MODE REGISTER (MR1[0] can be switched during initialization or later), the SDRAM is targeted, but not guaranteed to operate similarly to the NORMAL mode with a few notable exceptions: * * * The SDRAM supports only one value of CAS latency (CL=6) and one value of CAS WRITE latency (CWL=6). DLL DISABLE mode affects the READ data clock-to-data strobe relationship (tDQSCK), but not the READ data-to-data strobe relationship (tDQSQ, tQH). Special attention is needed to line the READ data up with the controller time domain when the DLL is disabled. In NORMAL operation (DLL on), tDQSCK starts from the rising clock edge AL + CL cycles after the READ command. In DLL DISABLE mode, tDQSCK starts AL = CL - 1 cycles after the READ command. Additionally, with the DLL disabled, the value of tDQSCK could be larger than tCK.
The ODT feature is not supported during DLL DISABLE mode (including dynamic ODT). The ODT resistors must be disabled by continuously registering the ODT ball LOW by programming RTT_NORM MR1[9,6,2] and RTT_WR MR2[10,9] to "0" while in DLL DISABLE mode. Specific steps must be followed to switch between the DLL enable and DLL DISABLE modes due to a gap in the allowed clock rates between the two modes (tCK[AVG]MAX and tCK[DLL DISABLE] MIN, respectively). The only time the clock is allowed to cross this clock rate gap is during SELF REFRESH mode. Thus, the required procedure for switching from the DLL ENABLE to DLL DISABLE mode is to change frequency curing self refresh (see Figure 34): 1. 2. 3. 4. 5. Starting from the IDLE state (all banks are PRECHARGED, all timings are fulfilled, ODT is turned off, and RTT_NOM and RTT_WR are HIGH-Z), set MR1[0] to "1" to DISABLE the DLL. Enter SELF REFRESH mode after tMOD has been satisfied. After tCKSRE is satisfied, change the frequency to the desired clock rate. SELF REFRESH may be exited when the clock is stabled with the new frequency for tCKSRX. The SDRAM will be ready for its next command in the DLL DISABLE mode after the greater of tMRD or tMOD has been satisfied. A ZQCL command should be issued with appropriate timing met as well.
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Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FIGURE 34 - DLL ENABLE MODE TO DLL DISABLE MODE
T0 CK# CK CKE Command MRS2 6 NOP t MOD SRE 3 NOP t CKSRE t CKESR ODT 9
Vali d 1 Vali d 1
T1
Ta0
Ta1
Tb0
Tc0
Td0
Td1
Te0
Te1
Tf0
SRX 4 7 t CKSRX 8
NOP t XS
MRS5
NOP t MOD
Vali d 1
NOTES: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Any valid command. Disable DLL by setting MR1[0] to "1." Wait tXS, then set MR1[0] to "0" to enable DLL. Wait tMRD, then set MR0[8] to "1" to begin DLL RESET.
Indicates a Break in Time Scale
Don 't Care
Wait tMRD, update registers (CL, CWL, and write recovery may be necessary). Wait tMOD, any valid command. Starting with the idle state. Change frequency. Clock must be stable at least tCKSRX. Static LOW in case RTT_NOM or RTT_WR is enabled; otherwise, static LOW or HIGH.
A similar procedure is required for switching from the DLL disable mode back to the DLL enable mode. This also requires changing the frequency during self refresh mode (see Figure 44 on page 100). 1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT is turned off, and RTT_NOM and RTT_WR are High-Z), enter self refresh mode. 2. After tCKSRE is satisfied, change the frequency to the new clock rate. 3. Self refresh may be exited when the clock is stable with the new frequency for tCKSRX. After tXS is satisfied, update the mode registers with the appropriate values. At a minimum, set MR1[0] to "0" to enable the DLL. Wait tMRD, then set MR0[8] to "1" to enable DLL RESET. 4. After another tMRD delay is satisfied, then update the remaining mode registers with the appropriate values. 5. The DRAM will be ready for its next command in the DLL enable mode after the greater of tMRD or tMOD has been satisfied. However, before applying any command or function requiring a locked DLL, a delay of tDLLK after DLL RESET must be satisfied. A ZQCL command should be issued with the appropriate timings met as well.
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Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FIGURE 35- DLL DISABLE MODE TO DLL ENABLE MODE
T0 CK# CK CKE
Ta0
Ta1
T b0
Tc0
Tc1
Td0
Te0
Tf0
Tg0
Th0
Vali d t DLLK
Command 7
NOP
1 SRE
NOP t CKSRE 8 t CKSRX 9
SRX2 t XS
MRS3 t MRD
MRS4 t MRD
MRS5
Vali d 6
ODTL off + 1 x t CK t CKESR ODT10
Indicates a Break in Time Scale
Don 't Care
NOTES: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Enter SELF REFRESH. Exit SELF REFRESH. Wait tXS, then set MR1[0] to "0" to enable DLL. Wait tMRD, then set MR0[8] to "1" to begin DLL RESET. Wait tMRD, update registers (CL, CWL, and write recovery may be necessary). Wait tMOD, any valid command. Starting with the idle state. Change frequency. Clock must be stable at least tCKSRX. Static LOW in case RTT_NOM or RTT_WR is enabled; otherwise, static LOW or HIGH.
The clock frequency range for the DLL disable mode is specified by the parameter tCKDLL_DIS. Due to latency counter and timing restrictions, only CL = 6 and CWL = 6 are supported. DLL disable mode will affect the read data clock to data strobe relationship (tDQSCK) but not the data strobe to data relationship (tDQSQ, tQH). Special attention is needed to the controller time domain. Compared to the DLL on mode where tDQSCK starts from the rising clock edge AL + CL cycles after the READ command, the DLL disable mode tDQSCK starts AL + CL - 1 cycles after the READ command (see Figure 45 on page 101). WRITE operations function similarly between the DLL enable and DLL disable modes; however, ODT functionality is not allowed with DLL disable mode.
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FIGURE 36 - DLL DISABLE tDQSCK TIMING
T0
CK# CK Command READ NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
Add ress
Vali d
RL = AL + C L = 6 (C L = 6, AL = 0) CL = 6
DQS, DQS# DLL on DQ BL8 DLL on DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7
RL (DLLdisable) = AL + (C L - 1) = 5 t DQSCK (DLL_DIS) MIN
DQS, DQS# DLL off DQ BL8 DLL disable DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7
t DQSCK (DLL DIS) MAX _
DQS, DQS# DLL off DQ BL8 DLL disable DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7
Transitioning Data
Don 't Care
INPUT CLOCK FREQUENCY CHANGE
When the DDR3 SDRAM is initialized, it requires the clock to be stable during most NORMAL states of operation. This means that after the clock frequency has been set to the stable state, the clock period is not allowed to deviate except what is allowed for by the clock jitter and spread spectrum clocking (SSC) specifications. The input clock frequency can be changed from one stable clock rate to another under two conditions: SELF REFRESH mode and PRECHARGE power-down mode. Outside of these two modes, it is illegal to change the clock frequency. For the SELF REFRESH mode condition, when the DDR3 SDRAM has been successfully placed into SELF REFRESH mode and tCKSRE has been satisfied, the state of the clock becomes a "Don't Care". When the clock becomes a "Don't Care", changing the clock frequency is permissible, provided the new clock frequency is stable prior to tCKSRX. When entering and exiting self refresh mode for the sole purpose of changing the clock frequency, the SELF REFRESH entry and exit specifications must still be met. The PRECHARGE power-down mode condition is when the DDR3 SDRAM is in PRECHARGE power-down mode (either fast exit mode or slow exit mode). Either ODT must be at a logic LOW or RTT_NOM and RTT_WR must be disabled via MR1 and MR2. This ensures RTT_NOM and RTT_WR are in an off state prior to entering PRECHARGE power-down mode while maintaining CKE at a logic LOW. A minimum of tCKSRE must occur after CKE goes LOW before the clock frequency can change. The DDR3 SDRAM input clock frequency is allowed to change only within the minimum and maximum operating frequency specified for the particular speed/temperature grade (tCK [AVG] MIN to tCK [AVG] MAX) device. During the input clock frequency change, CKE must be held at a stable LOW level. When the input clock frequency is changed, a stable clock must be provided to the SDRAM, tCKSRX before PRECHARGE power-down may be exited. After PRECHARGE power-down is exited and tXP has been satisfied, the DLL must be reset via the MRS. Depending on the new clock frequency, additional MRS commands may need to be issued. During the DLL lock time, RTT_NOM and RTT_WR must remain in an off state. After the DLL lock time, the SDRAM is ready to operate with a new clock frequency (period). This process is depicted in Figure 37.
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FIGURE 37- CHANGE FREQUENCY DURING PRECHARGE POWER-DOWN
Previous clock frequency T0 CK# CK t CH t CK t CKSRE t IH CKE t CPDED Command NOP NOP NOP t IS t CKE t IH t IS NOP t CKSRX t CL t CH
b
New clock fre quency Ta0 Tb0 Tc0 Tc1 Td0 Td1 Te0 Te1
T1
T2
t CL
b
t CH
b
t CL
b
t CH
b
t CL
b
t CK
b
t CK
b
t CK
b
NOP
MRS
NOP
Valid
Address
DLL RESET
Valid
t AOFPD/ t AOF ODT
t XP
t IH
t IS
DQS, DQS# DQ DM
High-Z High-Z
t DLLK Enter precharge power-down mode Frequency change Exit precharge power-down mode Indicates a Break in Time Scale
Don't Care
NOTES: 1.
2.
Applicable for both slow-exit and fast-exit precharge power-down modes.
tAOFPD
and tAOF must be satisfied and outputs High-Z prior to T1 (see "On-Die Termination
(ODT)" on page 161 for exact requirements). 3. If the RTT_NOM feature was enabled in the mode register prior to entering precharge power-down mode, the ODT signal must be continuously registered LOW ensuring RTT is in an off state. If the RTT_NOM feature was disabled in the mode register prior to entering precharge power-down mode, RTT will remain in the off state. The ODT signal can be registered either LOW or HIGH in this case.
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2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
WRITE LEVELING
For better signal integrity, DDR3 SDRAM memory sub-system designs have adopted use of fly-by topology for the commands, addresses, control signals and clocks. WRITE leveling is a scheme for the memory controller to de-skew the DQSx strobe (DQSx, DQSx\) to CK relationship at the SDRAM with a simple feedback feature provided it by the DDR3 SDRAM itself. WRITE leveling is generally used as part of the initialization process, if required. For NORMAL SDRAM operation, this feature must be disabled. This is the only SDRAM operation where the DQS functions as an input (to capture the incoming clock) and the DQs function as outputs (to report the stat of the clock). Note that nonstandard ODT schemes are required. The memory controller using the WRITE leveling procedure must have adjustable delay setting on its DQS strobe to align the rising edge of DQS to the clock at the SDRAM pins. This is accomplished when the SDRAM asynchronously feeds back the CK status via the DQ bus and samples with the rising edge of DQS. The controller repeatedly delays the DQS strobe until a CK transition from "0" to "1" is detected. The DQS delay established through this procedure helps ensure tDQSS, tDSS, and tDSH specifications in systems that use fly by topology by de-skewing the trace length mismatch. A conceptual timing of this procedure is shown in Figure 38.
FIGURE 38- WRITE LEVELING CONCEPT
T0 CK# CK
T1
T2
T3
T4
T5
T6
T7
Source
Differential DQS
Tn CK# CK
T0
T1
T2
T3
T4
T5
T6
Destination
Differential DQS
DQ
0
0
Destination
CK# CK
Tn
T0
T1
T2
T3
T4
T5
T6
Push DQS to capture 0-1 transition Differential DQS
DQ
1
1
Don't Care
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
WRITE LEVELING
When WRITE leveling is enabled, the rising edge of DQS samples CK and the rime DQ outputs the sampled CK's status. The prime DQ for each of the (4) words contained in the iMOD is DQ0 for the low byte, DQ8 for the high byte. It outputs the status of CK sampled by LDQSx and UDQSx. All other DQs (DQ[7:1], DQ[15:9] for the low word, DQ[23:17],DQ[31:25] for the next word, DQ[39:33], DQ[47:41] for the next and DQ[55:49], DQ[63:57] for the HIGH word) continue to drive LOW. Two prime DQ on each of the (4) words contained in the LDI iMOD allow each byte lane to be leveled independently.
WRITE LEVELING PROCEDURE
A memory controller initiates the SDRAM WRITE Leveling mode by setting the MR1[7] to a "1", assuming the other programmable features (MR0, MR1, MR2, and MR3) are first set and the DLL is fully reset and locked. The DQ balls enter the WRITE Leveling mode going from a "HIGH-Z" state to an undefined driving state so the DQ bus should not be driven. During WRITE Leveling mode, only the NOP and DES commands are allowed. The memory controller should attempt to level only one rank at a time; thus, the outputs of other ranks should be disabled by setting MR1[12] to a "1". The memory controller may assert ODT after a tMOD delay as the SDRAM will be ready to process the ODTL on delay (WL-2tCK), provided it does not violate the aforementioned tMOD delay requirement. The memory controller may drive LDQSx, UDQSx LOW and LDQSx\, UDQSx\ HIGH after tWLDQSEN has been satisfied. The controller may begin to toggle LDQSx, UDQSx after tWLMRD (one L[U]DQSs toggle is DQSs transitioning from a LOW state to a HIGH state with L[U]DQSx\ transitioning from a HIGH state to a LOW state, then both transition back to their original states). At a minimum, ODTL on and tAON must be satisfied at least one clock prior to DQS toggling. After tWLMRD and DQS LOW preamble (tWPRE) have been satisfied, the memory controller may provide either a single DQSx toggle or multiple DQSx toggles to sample CK for a given DQSx to CK skew. Each DQS toggle must not violate tDQSL (MIN) and tDQSH (MIN) specifications. tDQSL (MAX) and tDQSH (MAX) specifications are not applicable during WRITE leveling mode. The DQSx must be able to distinguish the CK's rising edge within tWLS and tWLH. The prime DQ will output the CK's status asynchronously from the associated DQSx rising edge CK capture within tWLO. The remaining DQs that always drive LOW when DQS is toggling must be LOW within tWLOE after the first tWLO is satisfied (the prime DQs going LOW). As previously noted, DQSx is an input and not an output during this process. Figure 39 depicts the basic timing parameters for the overall write leveling procedure. The memory controller will likely sample each applicable prime DQ state and determine whether to increment or decrement it DQS delay setting. After the memory controller performs enough DQSx toggles to detect the CK's "0-1" transition, the memory controller should lock the DQS delay setting for the SDRAM iMOD device. After locking the DQS setting, leveling for the rank will have been achieved, and the WRITE leveling mode for the rank should be disabled or reprogrammed (if WRITE leveling of another rank follows).
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FIGURE 39- WRITE LEVELING SEQUENCE
T1 t WLH CK# CK Command MRS1 NOP2 t MOD ODT t WLDQSEN Differential DQS4 t WLMRD Prime DQ 5 t WLO Early remaining DQ t WLO Late remaining DQ
t WLOE
T2 t WLS
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
t DQSL3
t DQSH3
t DQSL3
t DQSH3
t WLO
t WLO
Indicates a Break in Time Scale
Undefined Driving Mode
Don't Care
NOTES: 1. 2. 3. 4. 5. MRS: Load MR1 to enter write leveling mode. NOP: NOP or DES. DQS, DQS# needs to fulfill minimum pulse width requirements tDQSH (MIN) and tDQSL (MIN) as defined for regular writes. The maximum pulse width is system-dependent. Differential DQS is the differential data strobe (DQS, DQS#). Timing reference points are the zero crossings. The solid line represents DQS; the dotted line represents DQS#. DRAM drives leveling feedback on a prime DQ (DQ0 for x4 and x8). The remaining DQ are driven LOW and remain in this state throughout the leveling procedure.
WRITE LEVELING EXIT MODE
After the DDR3 SDRAM iMOD has been WRITE leveled, the controller must exit from WRITE Leveling mode before the NORMAL mode can be used. Figure 40 depicts a general procedure in exiting WRITE Leveling. After the last rising DQS (capturing a "1" at T0), the memory controller should stop driving the DQS signals after tWLO (MAX) delay plus enough delay to enable the memory controller to capture the applicable prime DQ state (at - Tb0). The DQ balls become undefined when DQS no longer remains LOW and they remain undefined until tMOD after the MRS command (at Te1). The ODT input should be deasserted LOW such that ODTL off (MIN) expires after the DQSx is no longer driving LOW. When ODT LOW satisfies tIS, ODT must be kept LOW (at -Tb0) until the SDRAM is ready for either another rank to be leveled or until the NORMAL mode can be used. After DQS termination is switched off, WRITE level mode should be disabled via the MRS command (at Tc2). After tMOD is satisfied (at Te1), any valid command may be registered by the SDRAM. Some MRS commands may be issued after tMRD (at Td1).
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FIGURE 40- EXIT WRITE LEVELING
T0 CK# CK Command NOP
T1
T2
Ta0
Tb0
Tc0
Tc1
Tc2
Td0
Td1
Te0
Te1
NOP
NOP
NOP
NOP
NOP
NOP
M RS
NOP t MRD
Valid
NOP
Valid
Add ress
MR1
Valid
Valid
t IS
ODT
t MOD t AOF (MIN)
ODTL off
RTT DQS, RTT DQS# DQS DQS# , RTT_DQ RTT_NOM
t AOF (MAX)
t WLO + t WLOE
DQ
CK = 1
Indicates a Break in Time Scale
Undefined Driving Mode
Transitioning
Don 't Care
Notes: 1. The DQ result, "= 1," between Ta0 and Tc0, is a result of the DQS, DQS# signals capturing CK HIGH just after the T0 state.
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81
High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
OPERATIONS
Initialization
The following sequence is required for power up and initialization, as shown in Figure 41. 1. Apply power. RESET\ is recommended to be below 0.2 x VccQ during power ramp to ensure the outputs remain disabled (HIGH-Z) and ODT off (RTT is also HIGH-Z). All other inputs, including ODT may be undefined. During power up, either of the following conditions may exist and must be met: * Condition A: * Vcc and VccQ are driven from a single power source and are ramped with a maximum delta voltage between them of V300mV. Slope reversal of any power supply signal is allowed. The voltage levels on all balls other than Vcc, VccQ, Vss and VssQ must be less than or equal to VccQ and Vcc on one side and must be greater than or equal to VssQ and Vss on the other side. * Both Vcc and VccQ power supplies ramp to Vcc (MIN) and VccQ (MIN) within tVccPR=200ms. * Both Vcc and VccQ power supplies ramp to Vcc (MIN) and VccQ (MIN) within tVccPR=200ms. * VREFDQ tracks Vcc x 0.5, VREFCA tracks Vcc x 0.5. * VTT is limited to 0.95V when the power ramp is complete and is not applied directly to the device; however, tVTD should be greater than or equal to zero to avoid device latchup. * Condition B: * Vcc may be applied before or at the same time as VccQ. * VccQ may be applied before or at the same time as VTT, VREFDQ and VREFCA. * No slope reversals are allowed in the power supply ramp for this condition. 2. Until stable power, maintain RESET\ LOW to ensure the outputs remain disabled (HIGH-Z). After the power is stable, RESET\ must be LOW for at least 200s to begin the initialization process. ODT will remain in the HIGH-Z state while RESET\ is LOW and until CKE is registered HIGH. CKE must be LOW 10ns prior to RESET\ transitioning HIGH. After RESET\ transitions HIGH, wait 500s (minus one clock) with CKE LOW. After this CKE LOW time, CKE may be brought HIGH (synchronously) and only NOP or DES commands may be issued. The clock must be present and valid for at least 10ns (and a minimum of five clocks) and ODT must be driven LOW at least tIS prior to CKE being registered HIGH. When CKE is registered HIGH, it must be continuously registered HIGH until the full initialization process is complete. After CKE is registered HIGH and after tXPR has been satisfied, MRS commands may be issued. Issue an MRS (LOAD MODE) command to MR2 with the applicable settings (provide LOW to BA2 and BA0 and HIGH to BA1). Issue an MRS command to MR3 with the applicable settings. Issue an MRS command to MR1 with the applicable settings, including enabling the DLL and configuring ODT. Issue and MRS command to MR0 with the applicable settings, including a DLL RESET command. tDLLK (512) cycles of clock input are required to lock the DLL. Issue a ZQCL command to calibrate RTT and RON values for the process voltage temperature (PVT). Prior to NORMAL operation. tZQINIT must be satisfied. When tDLLK and tZQINIT have been satisfied, the DDR3 SDRAM will be ready for normal operation.
3. 4. 5.
6. 7. 8. 9. 10. 11.
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Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FIGURE 41- INITIALIZATION SEQUENCE
T (MAX) = 200ms VCC VCCQ VTT VREF Power-up ramp t VTD CK# CK t CKSRX t IOz = 20ns RESET# T (MIN) = 10ns CKE t IS Valid t CL t CL Sta ble and vali d clo ck T0 t CK T1 Ta0 Tb0 Tc0 Td0 See power-up c onditions in the initialization sequence text, set up 1
ODT t IS Command NOP MRS MRS MRS MRS ZQCL
Valid
Valid
DM
Add ress
Code
Code
Code
Code
Valid
A10
Code
Code
Code
Code
A10 = H
Valid
BA[2:0]
BA0 = L BA1 = H BA2 = L
BA0 = H BA1 = H BA2 = L
BA0 = H BA1 = L BA2 = L
BA0 = L BA1 = L BA2 = L
Valid
DQS DQ
RTT
T = 200s (MIN)
T = 500s (MIN)
t XPR
t MRD
t MRD
t MRD
t MOD
t ZQ INIT
MR2 All voltage supplies vali d and stable
MR3
MR1 with DLL ena ble
MR0 with DLL reset
ZQ cali bration t DLLK Normal operation
DRAM ready for external commands
Indicates a Break in Time Scale
Don 't Care
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83
High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
MODE REGISTERS
Mode registers (MR0-MR3) are used to define various modes of programmable operation of the DDR3 SDRAM iMOD. A mode register is programmed via the MODE REGISTER SET (MRS) command during initialization and it retains the stored information (except for MR0[8] which is self-clearing) until it is either reprogrammed, RESET\ goes LOW, or until the device loses power. Contents of a mode register can be altered by re-executing the MRS command. If the user chooses to modify only a subset of the mode register's variables, all variables must be programmed when the MRS command is issued. Reprogramming the mode register will not alter the contents of the memory array, provided it is performed correctly. The MRS command can only be issued (or re-issued) when all banks are idle and in the PRECHARGED state (tRP is satisfied and no data bursts are in progress). After an MRS command has been issued, two parameters must be satisfied: tMRD and tMOD. The controller must wait tMRD before initiating any subsequent MRS commands (see Figure 42).
FIGURE 42- MRS-TO-MRS COMMAND TIMING (tMRD)
T0 CK# CK Command MRS1 NOP NOP t MRD Add ress Valid Valid NOP NOP MRS2 T1 T2 Ta0 Ta1 Ta2
CKE 3
Indicates a Break in Time Scale
NOTES: 1.
2.
Don 't Care
Prior to issuing the MRS command, all banks must be idle and precharged, tRP (MIN) must be satisfied, and no data bursts can be in progress.the leveling procedure.
tMRD
specifies the MRS-to-MRS command minimum cycle time.
3. 4.
CKE must be registered HIGH from the MRS command until tMRSPDEN (MIN) (see "Power-Down Mode" on page 153). For a CAS latency change, tXPDLL timing must be met before any nonMRS command.
The controller must also wait tMOD before initiating any nonMRS commands (excluding NOP and DES), as shown in Figure 52 on page 111. The DRAM requires tMOD in order to update the requested features, with the exception of DLL RESET, which requires additional time. Until tMOD has been satisfied, the updated features are to be assumed unavailable.
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FIGURE 43- MRS-TO-NONMRS COMMAND TIMING (tMOD)
T1 T2
t WLH
CK# CK Command MRS1 NOP2 NOP NOP NOP NOP NOP
t WLS
NOP
NOP
NOP
NOP
NOP
t MOD
ODT
t WLDQSEN
Differential DQS4
t DQSL3
t DQSH3
t DQSL3
t DQSH3
t WLMRD
Prime DQ 5
t WLO
t WLO
t WLO
Early remaining DQ
t WLOE
t WLO
Late remaining DQ
Indicates a Break in Time Scale
Undefined Driving Mode
Don't Care
NOTES: 1. 2. 3. Prior to issuing the MRS command, all banks must be idle (they must be precharged, tRP must be satisfied, and no data bursts can be in progress). Prior to Ta2 when tMOD (MIN) is being satisfied, no commands (except NOP/DES) may be issued. If RTT was previously enabled, ODT must be registered LOW at T0 so that ODTL is satisfied prior to Ta1. ODT must also be registered LOW at each rising CK edge from T0 until tMOD (MIN) is satisfied at Ta2. 4. CKE must be registered HIGH from the MRS command until tMRSPDEN (MIN), at which time power-down may occur (see "Power-Down Mode" on page 133).
MODE REGISTER 0 (MR0)
The base register, MR0 is used to define various DDR3 iMOD modes of operation. These definitions include the selection of a burst length, burst type, CAS latency, operating mode, DLL RESET, WRITE recovery and PRECHARGE power-down mode, as shown in Figure 44.
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
MODE REGISTER 0 (MR0) BURST TYPE
Accesses within a given burst may be programmed to either a sequential or an interleaved order. The burst type is selected via MR0[3], as shown in Figure 44. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 65. DDR3 only supports 4-bit burst chop and 8-bit burst access modes. Full interleaved address ordering is supported for READs, while WRITEs are restricted to nibble (BC4) or word (BL8) boundaries.
BURST LENGTH
Burst length is defined by MR0[1:0] (see Figure 44). READ and WRITE accesses to the DDR3 SDRAM iMOD are burst-oriented, with the burst length being programmable to "4" (chop mode). "8" (fixed burst), or selectable using A12 during a READ/WRITE command (on the fly). The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. When MR0[1:0] is set to "01" during a READ/WRITE command, if A12=0, then BC4 (chop) mode is selected. If A12=1, then BL8 mode is selected. Specific timing diagrams, and turnaround between READ/WRITE are shown in the READ/WRITE sections of this document. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A[i:2] when the burst length is set to "4" and by A[i:3] when the burst length is set to "8" (where Ai is the most significant column address bit for a given starting location within the block. The programmed burst length applies to both READ and WRITE bursts.
FIGURE 44- MODE REGISTER 0 (MR0) DEFINITIONS
BA2 BA 1 BA 0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address bus
16 15 14 13 12 11 10 WR 01 0 0 01 PD M15 M14 0 0 1 1 0 1 0 1 Mode Register Mode register 0 (MR0) Mode register 1 (MR1) Mode register 2 (MR2) Mode register 3 (MR3) M12 0 1 Precharge PD DLL off (slow exit) DLL on (fast exit)
9
8765432 DLL 01 CAS# latency BT 01
10 BL
Mode register 0 (MR0) M1 M0 0 0 1 0 1 Burst Length Fixed BL8 4 or 8 (on-the-fly via A12) Fixed BC4 (chop) Reserved
M8 DLL Reset 0 1 No Yes M6 M5 M4 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CAS Latency Reserved 5 6 7 8 9 10 11 M3 0 1
0 1 1
M11 M10 M9 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Write Recovery Reserved 5 6 7 8 10 12 Reserved
READ Burst Type Sequential (nibble) Interleaved
Notes:
1. MR0[16, 13, 7, 2] are reserved for future use and must be programmed to "0."
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
TABLE 65: BURST ORDER
Burst Length Read/Write Starting Column Address (A[2,1,0])
000 001 010 011 4 CHOP READ 100 101 110 111 0VV WRITE 1VV 000 001 010 8 READ 011 100 101 110 111 WRITE VVV
Burst Type (Decimal) Type = Sequential Type = Interleaved
0,1,2,3,Z,Z,Z,Z 1,2,3,0,Z,Z,Z,Z 2,3,0,1,Z,Z,Z,Z 3,0,1,2,Z,Z,Z,Z 4,5,6,7,Z,Z,Z,Z 5,6,7,4,Z,Z,Z,Z 6,7,4,5,Z,Z,Z,Z 7,4,5,6,Z,Z,Z,Z 0,1,2,3,X,X,X,X 4,5,6,7,X,X,X,X 0,1,2,3,4,5,6,7 1,2.3,0,5,6,7,4 2,3,0,1,6,7,4,5 3,0,1,2,7,4,5,6 4,5,6,7,0,1,2,3 5,6,7,4,1,2,3,0 6,7,4,5,2,3,0,1 7,4,5,6,3,0,1,2 0,1,2,3,4,5,6,7 0,1,2,3,Z,Z,Z,Z 1,0,3,2,Z,Z,Z,Z 2,3,0,1,Z,Z,Z,Z 3,2,1,0,Z,Z,Z,Z 4,5,6,7,Z,Z,Z,Z 5,4,7,6,Z,Z,Z,Z 6,7,4,5,Z,Z,Z,Z 7,6,5,4,Z,Z,Z,Z 0,1,2,3,X,X,X,X 4,5,6,7,X,X,X,X 0,1,2,3,4,5,6,7 1,0,3,2,5,4,7,6 2,3,0,1,6,7,4,5 3,2,1,0,7,6,5,4 4,5,6,7,0,1,2,3 5,4,7,6,1,0,3,2 6,7,4,5,2,3,0,1 7,6,5,4,3,2,1,0 0,1,2,3,4,5,6,7
Notes
1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,3,4 1,3,4 1 1 1 1 1 1 1 1 1,3
NOTES: 1. Internal READ and WRITE operations start at the same point in time for BC4 as they do for BL8.
2. 3.
Z = Data and Strobe output drivers in tri-state. X="Don't Care"
DLL RESET
DLL RESET is defined by MR0[8] (see Figure 44). Programming MR0[8] to "1" activates the DLL RESET function. MR0[8] is self-clearing, meaning it returns to a value of "0" after the DLL RESET function has been initiated. Anytime the DLL RESET function has been initiated, CKE must be HIGH and the clock held stable for 512 (tDLLK) clock cycles before a READ command can be issued. This is to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in invalid output timing specifications such as tDQSCK timings.
WRITE RECOVERY
WRITE RECOVERY time is defined by MR0[11:9] (see Figure 44). WRITE RECOVERY values of 5,6,7,8,10 or 12 may be used by programming MR0[11:9]. The user is required to program the correct value of WRITE RECOVERY and is calculated by dividing tWR (ns) by tCK (ns) and rounding up a non-integer value to the next integer: WR (cycles)=roundup (tWR[ns]/tCK [ns]).
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
PRECHARGE POWER-DOWN (PRECHARGE PD)
The PRECHARGE PD bit applies only when PRECHARGE power-down mode is being used. When MR0[12] is set to "0", the DLL is off during PRECHARGE power-down providing a lower standby current mode; however, tXPDLL must be satisfied when exiting. When MR0[12] is set to "1", the DLL continues to run during PRECHARGE power-down mode to enable a faster exit of PRECHARGE power-down mode; however, tXP must be satisfied when exiting (see Power-Down mode on Page 133).
CAS Latency (CL)
The CL is defined by MR0[6:4], as shown in Figure 44. CAS latency is the delay, as measured in clock cycles, between the internal READ command and the availability of the first bit of valid output data. The CL can be set to 5,6, 8, or 10. DDR3 SDRAM iMODs do not support half-clock latencies. Examples of CL=6 and CL=8 are shown in Figure 45 (below). If an internal READ command is registered at clock edge n, and the CAS latency is m clocks, the data will be available nominally coincident with clock edge n+m. Table 49 indicates the CLs supported at available operating frequencies.
FIGURE 45- READ LATENCY
T0 CK# CK Command READ NOP NOP NOP AL = 0, CL = 6 DQS, DQS# DI n DI n+1 DI n+2 DI n+3 DI n+4 NOP NOP NOP NOP NOP T1 T2 T3 T4 T5 T6 T7 T8
DQ
T0 CK# CK Command READ
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
NOP AL = 0, CL = 8
NOP
NOP
NOP
NOP
DQS, DQS# DI n
DQ
Transitioning Data
Don't Care
NOTES: 1. 2. For illustration purposes, only CL = 6 and CL = 8 are shown. Other CL values are possible. Shown with nominal tDQSCK and nominal tDSDQ.
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MODE REGISTER 1 (MR1)
The MODE REGISTER 1 (MR1) controls additional functions and features not available in the other mode registers; Q OFF (OUTPUT DISABLE), DLL ENABLE/DLL DISABLE, RTT_NOM value (ODT), WRITE LEVELING, POSTED CAS ADDITIVE latency, and OUTPUT DRIVE STRENGTH. These functions are controlled via the bits shown in Figure 46 below. The MR1 register is programmed via the MR5 command and retains the stored information until it is reprogrammed, until RESET\ goes LOW (true), or until the device loses power. Reprogramming the MR1 register will not alter the contents of the memory array, provided the operation is performed correctly. The MR1 register must be loaded when all banks are idle and no bursts are in progress. The controller must satisfy the specified timing parameters tMRD and tMOD before initiating a subsequent operation.
FIGURE 46- MODE REGISTER 1 (MR1) DEFINITION
BA2 BA 1 BA 0 A13 A12 A11 A10 A9 A 8 A7 A6 A5 A4 A3 A 2
A1 A0 Address bus
16 15 14 13 12 11 10 9 8 7 6 5 01 0 1 01 Q Off TDQS 01 RTT 01 WL RTT ODS M15 M14 0 0 1 1 0 1 0 1 Mode Register Mode register set 0 (MR0) Mode register set 1 (MR1) Mode register set 2 (MR2) Mode register set 3 (MR3) M9 M6 M2 000 001 011 101 110 111
M12 0 1 Q Off Enabled Disabled M11 0 1 TDQS Disabled Enabled
432 10 AL RTT ODS DLL
Mode register 1 (MR1) M0 0 1 DLL Enable Enable (normal) Disable
M5 M1 Output Drive Strength RTT_NOM (ODT)3 Writes RTT_NOM disabled M7 Write Levelization 0 1 Disable (normal) Enable 0 0 1 1 0 1 0 1 RZQ/6 (40 [NOM]) RZQ/7 (34 [NOM]) Reserved Reserved
RTT_NOM (ODT)2 Non-Writes RTT_NOM disabled RZQ/4 (60 [NOM]) RZQ/6 (40 [NOM]) RZQ/8 (30 [NOM]) Reserved Reserved
RZQ/4 (60 [NOM]) RZQ/6 (40 [NOM]) n/a n/a Reserved Reserved M4 M3 Additive Latency (AL) 0 0 1 1 0 1 0 1 Disabled (AL = 0) AL = CL - 1 AL = CL - 2 Reserved
0 1 0 RZQ/2 (120 [NOM]) RZQ/2 (120 [NOM]) 1 0 0 RZQ/12 (20 [NOM])
NOTES: 1. 2. 3. MR1[16, 13, 10, 8] are reserved for future use and must be programmed to "0." During write leveling, if MR1[7] and MR1[12] are "1" then all RTT_NOM values are available for use. During write leveling, if MR1[7] is a "1," but MR1[12] is a "0," then only RTT_NOM write values are available for use.
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
DLL ENABLE/DLL DISABLE
The DLL may be enabled or disabled by programming MR1[0] during the LOAD MODE command, as shown in Figure 46 (previous page). The DLL must be enabled for NORMAL operation. DLL ENABLE is required during power-up initialization and upon returning to NORMAL operation after having DISABLED the DLL for the purpose of debugging or evaluation. ENABLING the DLL should always be followed by resetting the DLL using the appropriate LOAD MODE command. If the DLL is enabled prior to entering SELF REFRESH mode, the DLL is automatically DISABLED when entering SELF REFRESH operation and is automatically RE-ENABLED and RESET upon exit of SELF REFRESH. If the DLL is DISABLED prior to entering SELF REFRESH, the DLL remains DISABLED even upon exit of the SELF REFRESH operation until it has been RE-ENABLED and RESET. The SDRAM is not tested, nor does LDI warrant compliance with NORMAL mode timings or functionality when the DLL is disabled. An attempt has been made for the SDRAM to operate in the NORMAL mode whenever possible when the DLL is disabled; however, by industry standards, the following exceptions have been observed, defined and listed: 1. ODT is NOT ALLOWED to be used 2. The OUTPUT DATA is no longer edge-aligned to the clock 3. CL and CWL can only be six clocks When the DLL is DISABLED, timing and functionality can vary from the NORMAL operational specifications when the DLL is enabled. DISABLING the DLL also implies the need to change the clock frequency.
ON-DIE TERMINATION (ODT)
ODT resistance RTT_NOM is defined by MR1[9,6,2] (see Figure 46). The RTT termination value applies to the DQx, LDMx, UDMx, L[U]DQSx and L[U]DQSx\. The DDR3 device architecture supports multiple RTT termination values based on RZQ/n where n can be 3,4,6,8 or 12 and RZQ is 240. Unlike DDR2, DDR3 ODT must be turned off prior to READING data out and must remain off during READ burst. RTT_NOM termination is allowed any time after the DRAM is initialized, calibrated, and not performing READ accesses, or in SELF REFRESH mode. Additionally, WRITE accesses with dynamic ODT enabled (RTT_WR) temporarily replaces RTT_NOM with RTT_WR. The actual effective termination, RTT_EFF, may be different from the RTT targeted value due to non-linearity of the termination. For RTT_EFF values and calculations, see the ON-DIE TERMINATION (ODT) description later in this DS. The ODT feature is designed to improve signal integrity of the memory device by enabling the DDR3 SDRAM controller to independently turn ON/ OFF ODT for any or all devices in the end designs array. The ODT input control pin is used to determine when RTT is turned on (ODTLon) and off (ODTLoff), assuming ODT has been ENABLED via MR1[9,6,2]. Timings for ODT are detailed in the "ON-DIE Termination (ODT)" description later in this DS.
OUTPUT DRIVE STRENGTH
The DDR3 SDRAM iMOD uses a programmable impedance output buffer. The drive strength mode register setting is defined by MR1[5:1], RZQ/7 (34 [NOM]) is the primary output driver impedance setting for the device. To calibrate the output driver impedance, and external precision resistor (RZQ) is connected between the ZQ ball and VssQ. The value of the resistor is 2401%. The output impedance is set during initialization. Additional impedance calibration updates do not affect device operation and all data sheet timings and current specifications are met during an update. To meet the 34 specification, the output drive strength must be set to 34 during initialization. To obtain a calibrated output driver impedance after power-up, the DDR3 iMOD SDRAM needs a calibration command that is part of the initialization and reset procedure.
WRITE LEVELING
The WRITE LEVELING function is enabled by MR1[7], as shown in Figure 46, WRITE LEVELING is used (during initialization) to de-skew the DQSx strobe to clock offset as a result of fly-by topology designs. For better signal integrity, some end use designs of DDR3 devices adopted fly-by topology for the commands, addresses, control signals and clocks. The fly-by topology benefits from a reduced number of stubs and their lengths, however, fly-by topology induces flight time skew between the clock and DQSx strobe (and DQx) at each SDRAM in the array. Controllers will have a difficult time maintaining tDQSS, tDSS and tDSH specifications without supporting WRITE LEVELING in systems which use fly-by topology based designs. WRITE LEVELING timing and detailed operation information is provided in "WRITE LEVELING.
OUTPUT ENABLE/DISABLE
The OUTPUT ENABLE function is defined by MR1[12], as shown in Figure 46. When enabled (MR1[12]=0), all outputs (DQx, DQSx, DQSx\) are tri-stated. The output DISABLE feature is intended to be used during Icc characterization of the READ current and during tDQSS margining (WRITE LEVELING) only.
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POSTED CAS ADDITIVE LATENCY (AL)
AL is supported to make the command and data bus efficient for sustainable bandwidths in DDR3 SRAMs. MR1[4,3] define the value of AL (see Figure 46). MR1[4,3] enables the user to program the DDR3 SDRAM with an AL=0, CL-1, or CL-2. With this feature, the DDR3 SDRAM enables a READ or WRITE command to be issued after the ACTIVATE command for that bank prior to tRCD(MIN). The only restriction is ACTIVATE to READ or WRITE + AL tRCD(MIN) must be satisfied. Assuming tRCD(MIN) = CL, a typical application using this feature, sets AL=CL - 1tCK = tRCD(MIN-1tCK. The READ or WRITE command is held for the time of the AL before it is released internally to the DDR3 SDRAM iMOD device. READ latency (RL) is controlled by the sum of the AL and CAS latency (CL), RL=AL+CL, WRITE latency (WL) is the sum of CAS WRITE latency and AL, WL=AL + CWL (see "MODE REGISTER 2 (MR2))". Examples of READ and WRITE latencies are shown in Figure 47 and Figure 49.
FIGURE 47- READ LATENCY (AL = 5, CL = 6)
BC4 T0 CK# CK Command ACTIVE n READ n t RCD (MIN) DQS, DQS# AL = 5 DQ RL = AL + CL = 11 CL = 6 DO n DO n+1 DO n+2 DO n+3 NOP NOP NOP NOP NOP NOP T1 T2 T6 T11 T12 T13 T14
Indicates a Break in Time Scale
Transitioning Data
Don't Care
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MODE REGISTER 2 (MR2)
The MODE REGISTER 2 (MR2) controls additional functions and features not available in the other mode registers. These additional functions are CAS WRITE latency (CWL), AUTO SELF REFRESH (ASR), SELF REFRESH TEMPERATURE (SRT) and DYNAMIC ODT (RTT_WR). These functions are controlled via the bits shown in Figure 48. The MR2 is programmed via the MRS command and will retain the stored information until it is programmed again or until the device loses power. Reprogramming the MR2 register will not alter the contents of the memory array, provided that the operation has been performed correctly. The MR2 register must be loaded when all banks are idle and no data bursts are in progress and the memory controller must wait for the specified time tMRD and tMOD before initiating a subsequent operation.
FIGURE 48- MODE REGISTER 2 (MR2) DEFINITION
A12
A10 A9 A8 A7 A 6 A5 A4 A3 A2 A1 A0
Address bus
9
8
7
6
5
4
3
2
1
0
Mode Register 2 (MR2)
M15 M14 0 0 1 1 0 1 0 1
Mode Register Mode register set 0 (MR0) Mode register set 1 (MR1) Mode register set 2 (MR2) Mode register set 3 (MR3)
Notes:
1. MR2[16, 13:11, 8, and 2:0] are reserved for future use and must all be programmed to "0."
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CAS WRITE LATENCY (CWL)
CWL is defined by MR2[5:3] and is the delay, in clock cycles, from the releasing of the internal WRITE to the latching of the first data in. CWL must be correctly set to the corresponding operating clock frequency (see Figure 48). The overall WRITE LATENCY (WL) is equal to CWL + AL (see Figure 46).
FIGURE 49- CAS WRITE LATENCY
BC4 T0 CK# CK Command ACTIVE n WRITE n t RCD (MIN) DQS, DQS# AL = 5 DQ WL = AL + CWL = 11 CWL = 6 DI n DI n+1 DI n+2 DI n+3 NOP NOP NOP NOP NOP NOP T1 T2 T6 T11 T12 T13 T14
Indicates A Break in Time Scale
Transitioning Data
Don't Care
AUTO SELF REFRESH (ASR)
Mode register MR2[6] is used to DISABLE/ENABLE the ASR function. When ASR is DISABLED, the SELF REFRESH mode's REFRESH rate is assumed to be at the normal 85C limit (commonly referred to as the 1X REFRESH rate). In the DISABLED mode, ASR requires the user to ensure the SDRAM never exceeds a Tc of 85C while in SELF REFRESH unless the user enables the SRT feature listed below, supporting an elevated temp up to +95C while in SELF REFRESH. The standard SELF REFRESH current test specifies test conditions to normal case temperature (85C) only, meaning if ASR is enabled, the standard SELF REFRESH current specification does not apply (see the "EXTENDED TEMPERATURE USAGE" description later in this DS).
optional extended temperature range of +95C while in SELF REFRESH mode. The standard SELF REFRESH current test specifies test conditions to normal case temperature (85C) only, meaning if SRT is enabled, the standard SELF REFRESH current specifications do not apply.
SRT vs. ASR
If the normal case temperature limit of 85C is not exceeded, then neither SRT nor ASR is required, and both can be DISABLED throughout operation. If the extended temperature option is used, the user is required to provide a 2X refresh rate during (manual) refresh for Extended temp devices or 3X refresh rate for Mil-temp devices. SRT and ASR should be enabled for automatic REFRESH services on all devices used in temperature environments 95C SRT forces the SDRAM to switch the internal SELF REFRESH rate from 1X to 2X. SELF REFRESH is performed at 2X regardless of Tc.
SELF REFRESH TEMPERATURE (SRT)
Mode register MR2[7] is used to DISABLE/ENABLE the SRT function. When SRT is Disabled, the SELF REFRESH mode's refresh rate is assumed to be at the normal 85C limit. In the DISABLED mode, SRT requires the user to ensure the SDRAM never exceeds the Tc limit of 85C while in SELF REFRESH mode unless the user enables ASR. When SRT is enabled, the SDRAM SELF REFRESH is changed internally from 1X to 2X, regardless of the case temperature (Tc). This enables the user to operate the SDRAM beyond the standard 85C limit up to the
ASR automatically switches the SDRAM's internal SELF REFRESH rate from 1X to 2X, however, while in SELF REFRESH mode, ASR enables the REFRESH rate automatically adjust between 1X and 2X REFRESH rate over the supported temperature range. One other disadvantage with ASR is the SDRAM cannot always switch from a 1X to a 2X refresh rate at an exact case Temperature of 85C. Although the SDRAM will support data integrity when it switches from a 1X to 2X rate, it may switch at a lower temperature than 85C. Since only one mode is necessary at one instant in time, SRT and ASR cannot be simultaneously enabled.
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DYNAMIC ODT
The dynamic ODT (RTT_WR) feature is defined by MR2[10,9]. Dynamic ODT is enabled when a value is selected. This new DDR3 feature enables the ODT termination value to change without issuing an MRS command, essentially changing the ODT termination "on-the-fly". With dynamic ODT (RTT_WR) when beginning a WRITE burst and subsequently switches back to ODT (RTT_WR) is enabled: ODTLCNW, ODTLCNW4, ODTLCNW* ODTH4, ODTH8 and tADC. Dynamic ODT is only applicable during WRITE cycles, If ODT (RTT_NOM) is disabled, dynamic ODT (RTT_WR) is still permitted. RTT_NOM and RTT_WR can be used independent of one another. Dynamic ODT is not available during WRITE LEVELING mode, regardless of the state of ODT (RTT_NOM). For details on ODT operation, refer to the "On-Die-Termination (ODT)" section.
MODE REGISTER (MR3)
The mode register 3 (MR3) controls additional functions and features not available via MR0, MR1 or MR2. Currently defined as the MULTIPURPOSE REGISTER (MPR). This function is controlled via the bits shown in Figure 50. The MR3 is programmed via the LOAD MODE command and retains the stored information until it is programmed again or until the device loses power. Reprogramming the MR3 register will not alter the contents of the memory array, provided the programming of the MR3 has been performed correctly. The MR3 register must be loaded when all banks are idle and no data bursts are in progress and the memory controller must wait the specified time tMRD and tMOD before initiating a subsequent operation.
FIGURE 50 - MODE REGISTER 3 (MR3) DEFINITION
BA2 BA 1 BA 0 A13 A12 A11 A10 A9
A8
A7 A 6 A5
A4 A3
A2
A1 A0
Address bus
16 01
15 14 13 12 11 10 9 87 6 54 3 2 10 1 1 01 01 01 01 01 01 01 01 01 01 01 MPR MPR_RF
Mode register 3 (MR3)
M15 M14 0 0 1 1 0 1 0 1
Mode Register Mo de register set (MR0) Mode register set 1 (MR1) Mode register set 2 (MR2) Mode register set 3 (MR3)
M2 0 1
MPR Enable Normal DRAM operations 2 Dataflow from MPR
M1 M0 0 0 1 1 0 1 0 1
MPR READ Function Predefined pattern 3 Reserved Reserved Reserved
NOTES: 1. 2. 3. MR3[16 and 13:4] are reserved for future use and must all be programmed to "0." When MPR control is set for normal DRAM operation, MR3[1, 0] will be ignored. Intended to be used for READ synchronization.
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MULTIPURPOSE REGISTER (MPR)
The MULTIPURPOSE REGISTER function is used to output a predefined system timing calibration bit sequence. Bit 2 is the master bit that enables or disables access to the MPR register and bits 1 and 0 determine which mode the MPR is placed in. The basic concept of the multipurpose register is shown in Figure 51. If MR3[2] is a "0", then the MPR access is disabled and the SDRAM operates in normal mode. However, if MR3[2] is a "1", then SDRAM no longer outputs normal read data but outputs MPR data as defined by MR3[0,1]. If MR3[0,1] is equal to "00", then a predefined read pattern for system calibration is selected. To enable the MPR, the MRS command is issued to MR3 and MR3[2]=1 (see Table 66). Prior to issuing the MRS command, all banks must be in the idle state (all banks are precharged, and tRP is met). When the MPR is enabled, any subsequent READ or RDAP commands are redirected to the multipurpose register. The resulting operation when either a READ or a RDAP command is issued is defined by MR3[1:0]when MPR is enabled (see Table 67). When the MPR is enabled, only READ or RDAP commands are allowed until a subsequent MRS command is issued with the MPR disabled (MR3[2]=0). POWER-DOWN, SELF REFRESH and any other NON READ or RDAP command is not allowed. The RESET function is supported during MPR enable mode.
FIGURE 51 - MULTIPURPOSE REGISTER (MPR) BLOCK DIAGRAM
Memory core
MR3[2] = 0 (MPR off)
Multipurpose register pre defined data for READs MR3[2] = 1 (MPR on) DQ, DM, DQ S, DQS#
NOTES: 1. 2. A predefined data pattern can be read out of the MPR with an external READ command. MR3[2] defines whether the data flow comes from the memory core or the MPR. When the data flow is defined, the MPR contents can be read out continuously with a regular READ or RDAP command.
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TABLE 66: BURST ORDER
MR3[2] MPR
0
MR3[1:0] MPR READ Function
"Don't Care"
Function
Normal Operation, no MPR transaction. All subsequent READs come from the SDRAM memory array. All subsequent WRITEs go to the SDRAM memory array.
1
A[1:0] (See Table 66)
Enable MPR mode, subsequent READ/RDAP commands defined by bits 1 and 2.
MPR FUNCTIONAL DESCRIPTION
The MPR JEDEC definition allows for either a prime DQ0 for lower byte and DQ8 for the upper byte of each of the (4) words contained in the LDI iMOD, to output the MPR data with the remaining DQs driven LOW, or for all DQs to output the MPR data. The MPR readout supports fixed READ burst and READ burst chop (MRS and OTF via A12/BC#) with regular READ latencies and AC timings applicable. This providing the DLL is locked as required. MPR addressing for a valid MPR READ is as follows: * A[1:0] must be set to "00" as the burst order is fixed per nibble * A2 selects the burst order * BL8, A2 is set to "0", and the burst order is fixed to 0,1,2,3,4,5,6,7 * For burst chop 4 cases, the burst order is switched on the nibble base and: * A2=0: burst order =0,1,2,3 * A2=1: burst order =4,5,6,7 * Burst order bit 0 (the first bit) is assigned to LSB, and burst order bit 7 (the last bit) is assigned to MSB * A[9:3] are a "Don't Care" * A10 is a "Don't Care" * A11 is a "Don't Care" * A12: Selects burst chop mode on-the-fly, if enabled within MR0 * A13 is a "Don't Care" * BA[2:0] are a "Don't Care"
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MPR REGISTER ADDRESS DEFINITIONS and BURSTING ORDER
The MPR currently supports a single data format. This data format is a predefined READ pattern for system calibration. The predefined pattern is always a repeating 0-1 bit pattern. Examples of the different type of predefined READ pattern bursts are shown in Figures 52, 53, and 54.
TABLE 67: BURST ORDER
MR3[2]
1
MR3[1:0]
00
Function
READ predefined pattern for system calibration
Burst Length
BL8
Read A[2:0]
000
Burst Order and Data Pattern
Burst Order: 0,1,2,3,4,5,6,7 Predefined pattern: 0,1,0,1,0,1,0,1
BC4
000
Burst Order: 0,1,2,3 Predefined pattern: 0,1,0,1
BC4 01
100
Burst Order: 4,5,6,7 Predefined pattern: 0,1,0,1
1
RFU
n/a n/a n/a
n/a n/a n/a n/a n/a n/a n/a n/a n/a
n/a n/a n/a n/a n/a n/a n/a n/a n/a
1
10
RFU
n/a n/a n/a
1
11
RFU
n/a n/a n/a
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Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 NOP NOP NOP NOP NOP NOP t MPRR MRS NOP 3 Vali d 0 00 0 0 0 0
Figure 52 - MPR System Read Calibration with BL8: Fixed Burst Order Single Readout
ADVANCE INFORMATION
T0 CK# CK Command t RP Bank add ress 02 02 Vali d 3 Vali d t MOD PREA NOP NOP MRS READ1
Ta0
Tb0
Tb1
Tc0
Tc9
Tc10
NOP
Valid
t MOD
A[1:0]
0
A2
1
A[9:3]
00
A 11 Vali d 1 Val i d
0
Val i d
A12/BC#
0
A [ 15:13]
0
RL DQS, DQS# DQ
Indicates a Break in Time Scale
Don 't Care
Notes:
1. READ with BL8 either by MRS or OTF. 2. Memory controller must drive 0 on A[2:0].
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A10/AP
1
0
Vali d
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Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 NOP NOP NOP NO NOP NOP NOP NOP RL
Figure 53 - MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout
ADVANCE INFORMATION
T0 CK# CK Command PREA t RP t MOD 3 0 1 00 1 0 0 0 Vali d Vali d Vali d 0 Vali d Vali d Vali d Vali d Vali d Vali d 1 Vali d RL DQS, DQS# 02 12 02 02 Vali d Vali d Bank add ress A[1:0] A2 A[9:3] A10/AP A11 A12/BC# A[15:13] t CC D MRS READ1 READ1
Ta
Tb
Tc0
Tc9
Tc10
Td
NOP
MRS
Vali d
t MPRR
t MOD
3
Vali d
0
00
0
0
0
0
DQ
Indicates a Break in Time Scale
Don 't Care
Notes:
1. READ with BL8 either by MRS or OTF. 2. Memory controller must drive 0 on A[2:0].
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Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Tc9 NOP NOP NOP NOP NOP NOP t MPRR MRS 3 Vali d 0 00 0 0 0 0 RL
Figure 54 - MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble
ADVANCE INFORMATION
T0 CK# CK Command NOP t RF t MOD 3 0 1 00 1 0 0 Vali d 1 Vali d Val i d 0 Val i d Vali d Vali d Vali d 1 Vali d RL DQS, DQS# Val i d Vali d 03 14 02 02 Vali d Vali d t CCD Bank add ress A[1:0] A2 A [ 9:3] A 10/A P A 11 A12/BC# A[15:13] 0 PREA MRS READ1 READ1
Ta
Tb
Tc0
Tc1
Tc10
Td
NOP
NOP
Valid
t MOD
Indicates a Break in Time Scale
Don 't Care
Notes:
1. 2. 3. 4.
READ with BC4 either by MRS or OTF. Memory controller must drive 0 on A[1:0]. A2 = 0 selects lower 4 nibble bits 0 . . . 3. A2 = 1 selects upper 4 nibble bits 4 . . . 7.
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Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 NOP NOP NOP NOP NOP NOP t MPRR MR S 3 Vali d 0 00 0 0 0 0 RL
Figure 55 - MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble
ADVANCE INFORMATION
T0 CK# CK Command t RF t MOD 3 0 1 00 1 0 0 0 Vali d 1 Val i d Val i d 0 Val i d Vali d Vali d Vali d 1 Vali d RL DQS, DQS# Val i d Vali d 13 04 02 02 Vali d Vali d t CCD Bank add ress A[1:0] A2 A [ 9:3] A 10/A P A 11 A12/BC# A [ 15:13] PREA MRS READ1 NOP READ1
Ta
Tb
Tc0
Tc1
Tc9
Tc10
Td
NOP
NOP
Valid
t MOD
DQ
Indicates a Break in Time Scale
Don 't Care
Notes:
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1. 2. 3. 4.
READ with BC4 either by MRS or OTF. Memory controller must drive 0 on A[1:0]. A2 = 1 selects upper 4 nibble bits 4 . . . 7. A2 = 0 selects lower 4 nibble bits 0 . . . 3.
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MPR READ PREDEFINED PATTERN
The predetermined READ calibration pattern is a fixed pattern of 0,1,0,1,0,1,0,1. The following is an example of using the READ out predetermined READ calibration pattern. The example is to perform multiple READS from the MULTIPURPOSE REGISTER (MPR) in order to do system level READ timing calibration based on the predetermined and standardized pattern. The following protocol outlines the steps used to perform the READ calibration: * Precharge all banks * After tRP is satisfied, set MRS, MR3[2] = 1 and MR3[1:0]=00. This redirects all subsequent READs and Loads the predefined pattern into the MPR. As soon as tMRD and tMOD are satisfied, the MPR is available. * Data WRITE operations are not allowed until the MPR returns to the normal SDRAM state * Issue a READ with burst order information (all other address pins are "Don't Care"): * A[1:0] = 00 (data burst order is fixed starting at nibble) * A2 = 0 (for BL8, burst order is fixed as 0,1,2,3,4,5,6,7) * A12 = 1 (use BL8) * After RL = AL + CL, the SDRAM bursts out the predefined READ calibration pattern (0,1,0,1,0,1,0,1) * The memory controller repeats the calibration READs until READ data capture at the memory controller is optimized * After the last MPR READ burst and after tMPRR has been satisfied, issue MRS, MR3[2] = 0 and MR3[1:0] = "Don't Care" to the normal SDRAM state. All subsequent READ and WRITE accesses will be regular READS and WRITES from/to the SDRAM array * When tMRD and tMOD are satisfied from the last MRS, the regular SDRAM commands (such as ACTIVATE a Memory bank for regular READ or WRITE access) are permitted
MODE REGISTER SET (MRS)
The mode registers are loaded via inputs BA[2:0], A[13:0]. BA[2:0] determines which mode register is programmed: * BA2 = 0, BA1 = 0, BA0 = 0 for MR0 * BA2 = 0, BA1 = 0, BA0 = 1 for MR1 * BA2 = 0, BA1 = 1, BA0 = 0 for MR2 * BA2 = 0, BA1 = 1, BA0 = 1 for MR3 The MRS command can only be issued (or reissued) when all banks are idle and in the precharged state (tRP is satisfied and no data bursts are in progress). The controller must wait the specified time tMRD before initiating a subsequent operation such as an ACTIVATE command. There is also a restriction after issuing an MRS command with regard to when the updated functions become available. This parameter is specified by tMOD. Both tMRD and tMOD parameters are shown in Figure 42 and 43. Violating either of these requirements will result in unspecified operation.
ZQ CALIBRATION
The ZQ CALIBRATION command is used to calibrate the SDRAM output drivers (RON) and ODT values (RTT) over process, voltage, and temperature, provided a dedicated 240 (1%) external resistor is connected from the SDRAM's ZQ ball to VssQ. DDR3 SDRAMs need a longer time to calibrate RON and ODT at power up INITIALIZATION and SELF REFRESH exit and a relatively shorter time to perform periodic calibrations. DDR3 SDRAM defines two ZQ CALIBRATION commands: ZQ CALIBRATION LONG (ZQCL) and ZQ CALIBRATION SHORT (ZQCS). An example of ZQ CALIBRATION timing is shown in Figure 56. All banks must be PRECHARGED and tRP must be met before ZQCL or ZQCS commands can be issued to the SDRAM. No other activities (other than another ZQCL or ZQCS command may be issued to the SDRAM) can be performed on the SDRAM array by the controller for the duration of tZQINIT or tZQOPER. The quiet time on the SDRAM array helps accurately calibrate RON and ODT. After SDRAM calibration is achieved, the SDRAM should disable the ZQ ball's current consumption path to reduce overall power usage. ZQ CALIBRATION commands can be issued in parallel to DLL RESET and locking time. Upon SELF REFRESH exit, an explicit ZQCL is required if ZQ CALIBRATION is desired. In dual rank system designs that share the ZQ resistor between devices, the controller must not allow overlap of tZQINT, tZQOPER or tZQCS between ranks.
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FIGURE 56 - ZQ CALIBRATION TIMING (ZQCL AND ZQCS)
CK# CK Command Address A10 CKE ODT DQ
T0
T1
Ta0
Ta1
Ta2
Ta3
Tb0
Tb1
Tc0
Tc1
Tc2
ZQCL
NOP
NOP
NOP
Valid Vali d Vali d
Vali d Vali d Vali d Vali d Vali d A ctivities
ZQCS
NOP
NOP
NOP
Valid Vali d Vali d
1 2 3 High-Z t ZQINIT or t ZQOPER
Vali d Vali d
1 2 3 High-Z t ZQCS
Vali d Vali d
Activities
Indicates a Break in Time Scale
Don 't Care
NOTES: 1. 2. 3. CKE must be continuously registered HIGH during the calibration procedure. ODT must be disabled via the ODT signal or the MRS during the calibration procedure. All devices connected to the DQ bus should be High-Z during calibration.
ACTIVATE
Before any READ or WRITE commands can be issued to a bank within the SDRAM, a ROW in that bank must be opened (ACTIVATED). This is accomplished via the ACTIVATE command, which selects both the BANK and the ROW to be ACTIVATED. After a ROW is opened with an ACTIVATE command, a READ or WRITE command may be issued to that ROW, subject to the tRCD specification. However, if the additive latency is programmed correctly, a READ or WRITE command may be issued prior to tRCD (MIN). In this operation, the SDRAM enables a READ or WRITE command to be issued after the ACTIVATE command for that bank, but prior to tRCD (MIN) (see "POSTED CAS ADDITIVE LATENCY (AL)). tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVATE command on which the READ or WRITE command can be entered. The same procedure is used to convert other specification limits from time units to clock cycles. When at least one bank is open, any READ-to-READ command delay or WRITE-to-WRITE command delay is restricted to tCCD (MIN). A subsequent ACTIVATE command to a different ROW in the same BANK can only be issued after the previous ACTIVE ROW has been closed (PRECHARGED). The minimum time interval between successive ACTIVATE commands to the same BANK is defined by tRC. A subsequent ACTIVATE command to another BANK can be issued while the first BANK is being accessed, which results in a reduction of total ROW-ACCESS overhead. The minimum time interval between successive ACTIVATE commands may be issued in a given tFAW (MIN) period, and the tRRD (MIN) restriction still applies. The tFAW (MIN) parameter applies, regardless of the number of BANKS already opened or closed.
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FIGURE 57 - EXAMPLE: MEETING tRRD (MIN) AND tRCD (MIN)
CK# CK Command
T0
T1
T2
T3
T4
T5
T8
T9
T10
T11
ACT
NOP
NOP
ACT
NOP
NOP
NOP
NOP
NOP
RD/WR
Add ress
Row
Row
Col
BA[2:0]
Bank x t RRD
Bank y t RCD
Bank y
Indicates a Break in Time Scale
Don 't Care
FIGURE 58 - EXAMPLE: tFAW
CK# CK Command Add ress
T0
T1
T4
T5
T8
T9
T10
T11
T19
T20
ACT
NOP
ACT
NOP
A CT
NOP
ACT
NOP
NOP
A CT
Row
Row
Row
Row
Row
BA[2:0]
Bank a t RRD
Bank b
Bank c
Bank d
Bank y e
t FAW
Indicates a Break in Time Scale
Don 't Care
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READ
READ bursts are initiated with a READ command. The starting COLUMN and BANK addresses are provided with the READ command and AUTO PRECHARGE is either enabled or disabled for that burst access. If AUTO PRECHARGE is enabled, the ROW being accessed is automatically PRECHARGED at the completion of the burst sequence. If AUTO PRECHARGE is disabled, the ROW will be left open after the completion of the burst. During READ bursts, the valid data out element from the starting column address is available at READ LATENCY (RL) clocks later. RL is defined as the sum of POSTED CAS ADDITIVE LATENCY (AL) and CAS LATENCY (CL) (RL = AL + CL). The value of AL and CL is programmable in the mode register via the MRS command. Each subsequent data-out element will be valid nominally at the next positive or negative clock edge (that is, at the next crossing of CK and CK\). Figure 59 shows an example of RL based on a CL setting of 8 as well as AL=0.
FIGURE 59 - READ LATENCY
T0 CK# CK Command Add ress READ Bank a, Col n CL = 8, AL = 0 DQS, DQS# DO n NOP NOP NOP NOP NOP NOP NOP T7 T8 T9 T10 T11 T12 T12
DQ
Indicates a Break in Time Scale
Transitioning Data
Don 't Care
Notes:
1. DO n = data-out from column n. 2. Subsequent elements of data-out appear in the programmed order following DO n. .
L[U]DQSx, L[U]DQSx\ is driven by the SDRAM along with the output data. The initial LOW state on L[U]DQSx and HIGH state on L[U]DQSx\, is known as the READ preamble (tRPRE). The LOW state on DQSx and the HIGH state on L[U]DQSx\, coincident with the last data-out element, is known as the READ postamble (tRPST). Upon completion of a burst, assuming no other commands have been initiated, the DQ will go HIGH-Z. A detailed explanation of tDQSQ (valid data-out skew), tQH (data-out window hold), and the valid data window are depicted in Figure 71. A detailed explanation of tDQSCK (DQS transition skew to CK) is also depicted in Figure 71. Data from any READ burst may be concatenated with data from a subsequent READ command to provide a continuous flow of data. The first data element from the new burst follows the last element of a completed burst. The new READ command should be issued tCCD cycles after the first READ command. This is shown for BL8 in Figure 60. If BC4 is enabled, tCCD must still be met which will cause a gap in the data output, as shown in Figure 61. Nonconsecutive READ data is reflected in Figure 62. DDR3 SDRAMs do not allow interrupting or truncating any READ burst. Data from any READ burst must be completed before a subsequent WRITE burst is allowed. An example of a READ burst followed by a WRITE burst for BL8 is shown in Figure 63. To ensure the READ data is completed before the WRITE data is on the bus, the minimum READ-to-WRITE timing is RL + tCCD - WL + 2tCK.
A READ burst may be followed by a PRECHARGE command to the same bank provided AUTO PRECHARGE is not ACTIVATED. The minimum READ-to-PRECHARGE command spacing to the same bank is four clocks and must also satisfy a minimum analog time from the READ command. This time is called tRTP (READ-to-PRECHARGE). tRTP starts AL cycles later than the READ command. Examples for BL8 are shown in Figure 65 and BC4 in Figure 66. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. The PRECHARGE command followed by another PRECHARGE command to the same bank is allowed. However, the precharge period will be determined by the last PRECHARGE command issued to the bank. If A10 is HIGH when a READ command is issued, the READ with AUTO PRECHARGE function is engaged. The SDRAM starts an AUTO PRECHARGE operation on the rising edge which is AL + tRTP cycles after the READ command. DDR3 SDRAMs support a tRAS lockout feature (see Figure 68). If tRAS (MIN) is not satisfied at the edge, the starting point of the AUTO PRECHARGE operation will be delayed until tRAS (MIN) is satisfied. In case the internal PRECHARGE operation is pushed out by tRTP, tRP starts at the point at which the internal PRECHARGE happens. The time from READ with AUTO PRECHARGE to the next ACTIVATE command the same bank is AL + (tRTP + tRP)*, where "*" means rounded up to the next integer. In any event, internal RECHARGE does not start earlier than four clocks after the last 8n-bit prefetch.
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High Performance, Integrated Memory Module Product
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High Performance, Integrated Memory Module Product
T5 T6 T7 T8 T9 T10 T11 NOP NOP NOP NOP NOP NOP NO P t RPRE
DO n DO n+1 DO n+2 DO n+3 DO n+4 DO n+5 DO n+6 DO n+7 DO b DO b+1 DO b+2 DO b+3 DO b+4
ADVANCE INFORMATION
T0 CK# CK Command 1 REA D t CCD Add ress 2
Bank, Col n Bank, Col b
T1
T2
T3
T4
T12
T13
T14
NOP
NOP
NOP
REA D
NO P
NOP
NOP
DQS, DQS# DQ3 RL = 5
Figure 60 - Consecutive READ Bursts (BL8)
DO b+5
DO b+6
DO b+7
RL = 5
Transitioning Data
Don 't Care
Notes:
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1. 2. 3. 4.
NOP commands are shown for ease of illustration; other commands may be valid at these times. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ command at T0 and T4. DO n (or b) = data-out from column n (or column b). BL8, RL = 5 (CL = 5, AL = 0).
106
t RPST
Jul 08, 2009 LDS-L9D320G32BG6-A
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
High Performance, Integrated Memory Module Product
T5 T6 T7 T8 T9 T10 T11 NOP NOP NOP NOP NOP NOP NOP t RPRE t RPST t RPRE t RPST
DO n DO n+1 DO n+2 DO n+3 DO b DO b+1 DO b+2 DO b+3
ADVANCE INFORMATION
T0 CK# CK Comman d 1 READ READ t CCD Address 2
Bank, Col n Bank, Col b
T1
T2
T3
T4
T12
T13
T14
NOP
NOP
NOP
NOP
NOP
NOP
DQS, DQS# DQ3 RL = 5
RL = 5
Figure 61 - Consecutive READ Bursts (BC4)
Transitioning Data
Don 't Care
Notes:
1. 2. 3. 4.
NOP commands are shown for ease of illustration; other commands may be valid at these times. The BC4 setting is activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during READ command at T0 and T4. DO n (or b) = data-out from column n (or column b). BC4, RL = 5 (CL = 5, AL = 0).
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T0 CK# CK Command Add ress Bank a, Col n READ NOP NOP NOP NOP READ Bank a, Col b CL = 8 CL = 8 DQS, DQS# DQ DO n DO b NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15
ADVANCE INFORMATION
T16
T17
NOP
NOP
Figure 62 - Nonconsecutive READ Bursts
Transitioning Data
Don 't Care
Notes:
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1. 2. 3. 4.
AL = 0, RL = 8. DO n (or b) = data-out from column n (or column b). Seven subse quent elements of data-out appear in the programmed order following DO n. Seven subse quent elements of data-out appear in the programmed order following DO b.
108
Jul 08, 2009 LDS-L9D320G32BG6-A
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
High Performance, Integrated Memory Module Product
T6 T7 T8 T9 T10 T11 T12 T13 WRITE NOP NOP NOP NOP NOP NOP NOP t BL = 4 clocks
Bank, Col b
ADVANCE INFORMATION
CK# CK Command 1 READ NOP NOP NOP NOP NOP
T0
T1
T2
T3
T4
T5
T14
T15
NOP
NOP
READ-to-WRITE command delay = RL + t CCD + 2t CK - WL
t WR
t WTR
Add ress 2
Bank, Col n
t RPRE DQS, DQS# DQ3
DO n DO n+1 DO n+2 DO n+3 DO n+4 DO n+5 DO n+6
t RP ST
t WPRE
t WPST
DO n+7
DI n
DI n+1
DI n+2
DI n+3
DI n+4
DI n+5
DI n+6
DI n+7
Figure 63 - READ (BL8) to WRITE (BL8)
RL = 5
WL = 5
Transitioning Data
Don 't Care
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Notes:
1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the READ command at T0, and the WRITE command at T6.
109
Jul 08, 2009 LDS-L9D320G32BG6-A
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
High Performance, Integrated Memory Module Product
T5 T6 T7 T8 T9 T10 T11 T12 T13 NOP NOP NOP NOP NOP NOP NOP NOP NOP t BL = 4 clo cks t RPST t WPRE t WPST
DO n DO n +1 DO n +2 DO n+ 3 DI n DI n +1 DI n +2 DI n +3
ADVANCE INFORMATION
CK# CK Command 1 READ NOP NOP NOP WRITE
T0
T1
T2
T3
T4
T14
T15
NOP
NOP
READ-to-WRITE command delay = RL + t CC D/2 + 2 t CK - WL
t WR t WTR
Add ress2
Bank, Col n
Bank, Col b
t RPRE DQS, DQS# DQ3
Figure 64 - READ (BC4) to WRITE (BC4) OTF
RL = 5 WL = 5
Transitioning Data
Don 't Care
Notes:
LOGIC Devices Incorporated
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1. 2. 3. 4.
NOP commands are shown for ease of illustration; other commands may be valid at these times. The BC4 OTF setting is activated by MR0[1:0] and A12 = 0 during READ command at T0 and WRITE command at T4. DO n = data-out from column n; DI n = data-in from column b. BC4, RL = 5 (AL - 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
110
Jul 08, 2009 LDS-L9D320G32BG6-A
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
High Performance, Integrated Memory Module Product
T6 T7 T8 T9 T10 T11 T12 T13 WRITE NOP NOP NOP NOP NOP NOP NOP t BL = 4 clocks
Bank, Col b
ADVANCE INFORMATION
CK# CK Command 1 READ NOP NOP NOP NOP NOP
T0
T1
T2
T3
T4
T5
T14
T15
NOP
NOP
READ-to-WRITE command delay = RL + t CCD + 2t CK - WL
t WR
t WTR
Add ress 2
Bank, Col n
t RPRE DQS, DQS# DQ3 RL = 5
DO n DO n+1 DO n+2 DO n+3 DO n+4 DO n+5 DO n+6
t RP ST
t WPRE
t WPST
DO n+7
DI n
DI n+1
DI n+2
DI n+3
DI n+4
DI n+5
DI n+6
DI n+7
WL = 5
Figure 65 - READ to PRECHARGE (BL8)
Transitioning Data
Don 't Care
Notes:
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1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the READ command at T0, and the WRITE command at T6. 3. DO n = data-out from column, DI b = data-in for column b. 4. BL8, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
111
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L9D320G32BG6
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
Figure 66 - READ to PRECHARGE (BC4)
DQS, DQS#
Command
Add ress
C K#
CK
DQ
Bank a, Col n
READ NOP NOP
T0 T1 T2
t RAS
DO n DO n+1 DO n+2 DO n+3
t RTP
NOP NOP
Bank a, (or all)
T3 T4
PRE NOP NOP NOP NOP
T5 T6 T7 T8
t RP
Bank a, Row b
T9
NOP NOP NOP ACT NOP NOP
T10 T11 T12 T13 T14 T15
Transitioning Data Don 't Care
NOP NOP
T16 T17
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Figure 67 - READ to PRECHARGE (AL = 5, CL = 6)
BC4 DQS, DQS#
Command
CK#
DQ AL = 5 RL = AL + CL = 11 CL = 6
CK
ACTIVE n READ n t RCD (MIN) NOP NOP NOP
T0 T1 T2 T6 T11
Indicates a Break in Time Scale Transitioning Data Don't Care
NOP
T12
DO n DO n+1 NOP T13 DO n+2 DO n+3 NOP
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T14
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L9D320G32BG6
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Figure 68 - READ with Auto Precharge (AL = 4, CL = 6)
DQS, DQS# Command Add ress
CK#
DQ
CK
Bank a, Col n
READ NOP
T0 T1
AL = 4 t RTP (MIN)
NOP NOP NOP NOP NOP
T2 T3 T4 T5 T6
t RAS (MIN) CL = 6
DO n DO n+1 DO n+2 DO n+3
NOP NOP NOP NOP NOP
T7 T8 T9 T10 T11
Indicates A Break in Time Scale Transitioning Data Don 't Care t RP
NOP NOP NOP
Bank a, Row b
T12 T13
ACT
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Ta0
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L9D320G32BG6
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READ
A DQSx to DQ output timing is shown in Figure 69. The DQ transitions between valid data outputs must be within tDQSQ of the crossing point of L[U]DQSx, L[U]DQSx\. DQS must also maintain a minimum HIGH and LOW time of tQSH and tQSL. Prior to the READ preamble, the DQ balls will either be floating or terminated depending on the status of the ODT signal. Figure 70 shows the strobe-to-clock timing during a READ. The crossing point DQSx, DQSx\ must transition with tDQSCK of the clock crossing point. The data out has no timing relationship to clock, only to DQS, as shown in Figure 70. Figure 70 also shows the READ preamble and postamble. Normally, both DQSx and DQSx\ are HIGH-Z to save power (VccQ). Prior to data output from the SDRAM, DQSx is driven LOW and DQSx\ driven HIGH for tRPRE. This is known as the READ preamble. The READ postamble, tRPST, is one half clock from the last L[U]DQSx, L[U]DQSx\ transition. During the READ postamble, L[U]DQSx is driven LOW and L[U] DQSx\ driven HIGH. When complete, the DQ will either be disabled or will continue terminating depending on the state of the ODT signal. Figure 75 demonstrates how to measure tRPST.
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T3 T4 T5 T6 T7 T8 NOP NOP NOP NOP NOP NOP t DQSQ (MAX) t LZ (DQ) MIN t DQSQ (MAX) t RPRE t QH DO n DO n
DO n DO n+1 DO n+2 DO n+3 DO n+4 DO n+5 DO n+6
ADVANCE INFORMATION
CK# CK Command 1 READ RL = AL + CL NOP NOP
T0
T1
T2
T9
T10
NOP
NOP
Figure 69 - Data Output Timing - tDQSQ and Data Valid Window
Add ress 2
Bank, Col n
t RPST
t HZ (DQ) MAX
DQS, DQS# DQ3 (last data valid) DQ3 (first data no lon ger valid) All DQ collectively
DO n+7
Data valid
Data valid
Transitioning Data
Don 't Care
Notes:
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1. 2. 3. 4. 5. 6. 7.
NOP commands are shown for ease of illustration; other commands may be valid at these times. The BL8 setting is activated by either MR0[1, 0] = 0, 0 or MR0[0, 1] = 0, 1 and A12 = 1 during READ command at T0. DO n = data-out from column n. BL8, RL = 5 (AL = 0, CL = 5). Output timings are referenced to VCCQ/2 and DLL on and locked. t DQSQ defines the skew between DQS, DQS# to data and does not define DQS, DQS# to clock. Early data transitions may not always happen at the same DQ. Data transitions of a DQ can vary (either early or late) within a burst.
116
t QH DO DO DO DO DO DO DO n+1 n+2 n+3 n+4 n+5 n+6 n+7 DO DO DO DO DO DO DO n+3 n+1 n+2 n+4 n+5 n+6 n+7
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L9D320G32BG6
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OUTPUT TIMING
tHZ
and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which specifies when the device output is no longer driving tHZ (DQS) and tHZ (DQ) or begins driving tLZ (DQS). tLZ (DQ), Figure 71 shows a method to calculate the point when the device is not longer driving tHZ (DQS) and tHZ (DQ) or begins driving tLZ (DQS), tLZ (DQ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. The parameters tLZ (DQS), tLZ (DQ), tHZ (DQS) and tHZ (DQ) are defined as single-ended.
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T2 T3 T4 t DQSCK(MIN) t DQSCK(MIN) t DQSCK(MIN) t QSL t QSH t QSL Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 t DQSCK(MAX) t DQSCK(MAX) t DQSCK(MAX) t QSH t QSL t QSH t QSL Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6
ADVANCE INFORMATION
RL measured to this point T0 CK CK# t DQSCK(MIN) t LZ (DQS)MIN DQS, DQS# early strobe t RPRE Bit 0 t LZ (DQS)MAX T1
T5
T6
t HZ (DQS) MIN
t QSH
t RPST
t HZ (DQS) MAX t DQSCK(MAX)
t RPST
Figure 70 - Data Strobe Timing - READs
DQS, DQS# late strobe t RPRE
Bit 7
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L9D320G32BG6
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L9D320G32BG6
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Figure 71 - Method for Calculating tLZ and tHZ
VOH - xmV VOH - 2xmV t HZ (DQS), t HZ (DQ) VOL + 2xmV VOL + xmV
VTT + 2xmV VTT + xmV t LZ (DQS), t LZ (DQ) VTT - xmV VTT - 2xmV
T2 T1
T1 T2
t HZ (DQS),t HZ (DQ) end point = 2 x T1 - T2
t LZ (DQS),t LZ (DQ) begin point = 2 x T1 - T2
Notes:
1. Within a burst, the rising strobe edge is not necessarily fixed at t DQSCK (MIN) or t DQSCK (MAX). Instead, the rising strobe edge can vary between t DQSCK (MIN) and t DQSCK (MAX). 2. The DQS high pulse width is defined by t QSH, and the DQS low pulse width is defined by t QSL. Likewise, t LZ (DQS) MIN and t HZ (DQS) MIN are not tied to t DQSCK (MIN) (early strobe case) and t LZ (DQS) MAX and t HZ (DQS) MAX are not tied to t DQSCK (MAX) (late strobe case); however, they tend to track one another. 3. The minimum pulse width of the READ preamble is defined by t RPRE (MIN). The minimum pulse width of the READ postamble is defined by t RPST (MIN).
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FIGURE 72 - tRPRE TIMING
CK VTT CK# tA DQS Single-ended signal, provided as background information tC DQS# Single-ended signal, provided as background information T1 t RPRE begins DQS - DQS# Resultin g differential signal relevant for t RPRE specification t RPRE T2 t RPRE ends 0V tD VTT tB VTT
FIGURE 73 - tRPST TIMING
CK VTT CK#
tA DQS Single-ended signal, provided as background information tC DQS# Single-ended signal, provided as background information tB VTT
tD VTT
DQS - DQS# Resultin g differential signal relevant for t RPST specification T1 t RPST begins
t RPST 0V
T2 t RPST ends
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120
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Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FIGURE 74 - tWPRE TIMING
CK VTT CK#
T1 t WPRE begins DQS - DQS# Resulting differential signal relevant for t WPRE specification 0V T2 t WPRE ends
t WPRE
FIGURE 75 - tWPST TIMING
CK VTT CK#
t WPST DQS - DQS# Resulting differential signal relevant for t WPST specification T1 t WPST begins T2 t WPST ends 0V
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Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
WRITE
WRITE bursts are initiated with a WRITE command. The starting COLUMN and BANK addresses are provided with the WRITE command, and AUTO PRECHARGE is selected, the ROW being accessed will be PRECHARGED at the end of WRITE burst. If AUTO PRECHARGE is not selected, the ROW will remain open for subsequent accesses. After a WRITE command has been issued, the WRITE burst may not be interrupted. For the generic WRITE commands used in Figure 76 though Figure 84, AUTO PRECHARGE is disabled. During WRITE bursts, the first valid data-in element is registered on a rising edge of DQSx following the WRITE LATENCY (WL) clocks later and subsequent data elements will be registered on successive edges of DQSx. WRITE LATENCY (WL) is defined as the sum of POSTED CAS ADDITIVE LATENCY (AL) and CAS WRITE LATENCY (CWL): WL = AL + CWL. The values of AL and CWL are programmed in the MR- and MR2 registers, respectively. Prior to the first valid DQSx edge, a full cycle is needed (including a dummy crossover of DQSx, DQSx\) and specified as the WRITE preamble shown in Figure 76. The half cycle on DQSx following the last data-in element is known as the WRITE postamble. The time between the WRITE command and the first valid edge of DQSx is WL clocks tDQSS. Figure 77 through Figure 84 show the nominal case where tDQSS = 0ns; however, Figure 76 includes tDQSS (MIN) and tDQSS (MAX) cases. Data may be masked from completing a WRITE using data mask. The mask occurs on the DM ball aligned to the WRITE data. If DM is LOW, the WRITE completes normally. If DM is HIGH, that bit of data is masked. Upon completion of a burst, assuming no other commands have been initiated, the DQ will remain HIGH-Z and any additional input data will be ignored. Data for any WRITE burst may be concatenated with a subsequent WRITE command to provide a continuous flow of input data. The new WRITE command can be tCCD clocks following the previous WRITE command. The first data element from the new burst is applied after the last element of a completed burst. Figures 77 and 78 show concatenated bursts. An example of nonconsecutive WRITES is shown in Figure 79. Data for any WRITE burst may be followed by a subsequent READ command after tWTR has been met (see Figures 80, 81 and 82). Data for any WRITE burst may be followed by a subsequent PRECHARGE command providing tWR has been met, as shown in Figure 83 and Figure 84. Both tWTR and tWR starting time may vary depending on the mode register settings (fixed BC4, BL8 vs. OTF).
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FIGURE 76 - WRITE BURST
T0 CK# CK Command 1 WRITE
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
NOP
NOP WL = AL + CWL
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Address 2
Bank, Col n
t DQSS t DSH t DQSS(MIN) DQS, DQS# t DQSH t DQSL t DQSH t WPRE
t DSH
t DSH
t DSH t WPST
t DQSL t DQSH
t DQSL t DQSH
t DQSL t DQSH
t DQSL
DQ3
DI n
DI n+1
DI n+2
DI n+3
DI n+4
DI n+5
DI n+6
DI n+7
t DSH t DQSS(NOM) DQS, DQS# t DQSH t DQSL t DSS DQ3 DI n t DQSH t WPRE
t DSH
t DSH
t DSH t WPST
t DQSL t DQSH t DSS
t DQSL t DQSH t DSS
t DQSL t DQSH t DSS
t DQSL t DSS
DI n+1
DI n+2
DI n+3
DI n+4
DI n+5
DI n+6
DI n+7
t DQSS
t DQSS(MAX) DQS, DQS#
t WPRE
t WPST
t DQSH
t DQSL t DQSH t DSS
t DQSL t DQSH t DSS
t DQSL t DQSH t DSS
t DQSL t DQSH t DSS
t DQSL t DSS
DQ3
DI n
DI n+1
DI n+2
DI n+3
DI n+4
DI n+5
DI n+6
DI n+7 Transitioning Data Don 't Care
Notes:
1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the WRITE command at T0. 3. DI n = data-in for column n. 4. BL8, WL = 5 (AL = 0, CWL = 5). 5. t DQSS must be met at each rising clock edge. 6. t WPST is usually depicted as ending at the crossing of DQS, DQS#; however, t WPST actually ends when DQS no longer drives LOW and DQS# no longer drives HIGH.
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FIGURE 77 - CONSECUTIVE WRITE (BL8) TO WRITE (BL8)
T0 C K# CK Command 1 WRITE
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
NOP
NOP t CCD
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP t BL = 4 clocks
NOP
NOP t WR
NOP t WTR
Add ress 2
Valid
Valid t WPST
t WPRE DQS, DQS# DQ3 WL = 5 WL = 5 DI n DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6
DI b+7
Transitioning Data
Don 't Care
Notes:
1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the WRITE commands at T0 and T4. 3. DI n (or b) = data-in for column n (or column b). 4. BL8, WL = 5 (AL = 0, CWL = 5).
FIGURE 78 - CONSECUTIVE WRITE (BC4) TO WRITE (BC4) VIA MRS OR OTF
T0 C K# CK Command 1 WRITE
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
NOP
NOP t CCD
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP t BL = 4 clo cks
NOP
NOP t WR
NOP t WTR
Address2
Vali d
Vali d
t WPRE DQS, DQS# DQ3 WL = 5 DI n DI n+1 DI n+2
t WPST
t WPRE
t WPST
DI n+3
DI b
DI b+1
DI b+2
DI b+3
WL = 5 Transitioning Data Don 't Care
Notes:
1. 2. 3. 4.
NOP commands are shown for ease of illustration; other commands may be valid at these times. BC4, WL = 5 (AL = 0, CWL = 5). DI n (or b) = data-in for column n (or column b). The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0 and T4.
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124
High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FIGURE 79 - NONCONSECUTIVE WRITE TO WRITE
T0 C K# CK C ommand Add ress WRITE Vali d
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
NOP
NOP
NOP
NOP
WRITE Vali d
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
WL = C WL + AL = 7 WL = C WL + AL = 7 DQS, DQS# DQ DM DI n DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7
Transitioning Data
Don't Care
Notes:
1. 2. 3. 4.
DI n (or b) = data-in for column n (or column b). Seven subsequent elements of data-in are applied in the programmed order following DO n. Each WRITE command may be to any bank. Shown for WL = 7 (CWL = 7, AL = 0).
FIGURE 80 - WRITE (BL8) TO READ (BL8)
T0 CK# CK Command 1 WRITE
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
Ta0
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP t WTR 2
NOP
READ
Add ress3
Vali d t WPRE t WPST
Vali d
DQS, DQS# DQ4 WL = 5 Indicates a Break in Time Scale DI n DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7
Transitioning Data
Don 't Care
Notes:
1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. t WTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last write data shown at T9. 3. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and MR0[12] = 1 during the WRITE command at T0. The READ command at Ta0 can be either BC4 or BL8, depending on MR0[1:0] and the A12 status at Ta0. 4. DI n = data-in for column n. 5. RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
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2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
High Performance, Integrated Memory Module Product
T4 T5 T6 T7 T8 NOP NOP NOP NOP NOP t WPRE t WPST DI n DI n+1 DI n+2 DI n+3 Indicates a Break in Time Scale
ADVANCE INFORMATION
T0 T3 CK# CK Command 1 WRITE NOP NOP NOP
T1
T2
T9
Ta0
NOP
READ
t WTR 2
FIGURE 81 - WRITE TO READ (BC4 MODE REGISTER SETTING)
Add ress3
Vali d
Vali d
DQS, DQS# DQ 4 WL = 5
Transitioning Data
Don 't Care
Notes:
1. NOP commands are shown for ease of illustrati on; other commands may be valid at these times. 2. t WTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last write data shown at T7. 3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0 and the READ command at Ta0. 4. DI n = data-in for column n. 5. BC4 (fixed), WL = 5 (AL = 0, CWL = 5), RL = 5 (AL = 0, CL = 5).
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Jul 08, 2009 LDS-L9D320G32BG6-A
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
High Performance, Integrated Memory Module Product
T4 T5 T6 T7 T8 T9 T10 NOP NOP NOP NOP t BL = 4 clo cks NOP NOP NOP t WPRE t WPST DI n DI n+1 DI n+2 DI n+3
ADVANCE INFORMATION
T0 CK# CK C ommand 1 WRITE NOP NOP NOP
T1
T2
T3
T11
Tn
NOP
READ
t WTR 2
Add ress 3 Vali d
Vali d
FIGURE 82 - WRITE (BC4 OTF) TO READ (BC4 OTF)
DQ 4 WL = 5
RL = 5
Indicates a Break in Time Scale
Transitioning Data
Don 't Care
Notes:
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1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. t WTR controls the WRITE-to -READ delay to the same device and starts after t BL. 3. The BC4 OTF setting is activated by MR0[1:0] = 01 and A 12 = 0 during the WRITE command at T0 and the READ command at Tn. 4. DI n = data-in for column n. 5. BC4, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
127
DQS, DQS#
Jul 08, 2009 LDS-L9D320G32BG6-A
L9D320G32BG6
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FIGURE 83 - WRITE (BL8) TO PRECHARGE
CK# CK
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
Ta0
Ta1
Command
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
PRE
Add ress
Vali d WL = AL + CWL t WR
Vali d
DQS, DQS# DQ BL8 DI n DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7
Indicates a Break in Time Scale
Transitioning Data
Don 't Care
Notes:
1. DI n = data-in from column n. 2. Seven subsequent elements of data-in are applie d in the programmed order following DO n. 3. Shown for WL = 7 (AL = 0, CWL = 7).
FIGURE 84 - WRITE (BC4 MODE REGISTER SETTING) TO PRECHARGE
CK# CK
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
Ta0
Ta1
Comman d
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
PRE
Add ress
Vali d WL = AL + CWL t WR
Vali d
DQS, DQS# DQ BC4 DI n DI n+ 1 DI n+ 2 DI n+ 3
Indicates a Break in Time Scale
Transitioning Data
Don 't Care
Notes:
1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The write recovery time ( t WR) is referenced from the first rising clock edge after the last write data is shown at T7. t WR specifies the last burst WRITE cycle until the PRECHARGE command can be issued to the same bank. 3. The fixed BC4 setting is activated by MR0[ 1:0] = 10 during the WRITE command at T0. 4. DI n = data-in for column n. 5. BC4 (fixed), WL = 5, RL = 5.
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FIGURE 85 - WRITE (BC4 OTF) TO PRECHARGE
T0 CK# CK Command 1 T1 T2 T3 T4 T5 T6 T7 T8 T9 Tn
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP t WR2
PRE
Add ress 3
Bank, Col n t WPRE t WPST
Valid
DQS, DQS # DQ4 WL = 5 DI n DI n+1 DI n+2 DI n+3
Indicates a Break In Time Scale
Transitioning Data
Don 't Care
Notes:
1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The write recovery time ( t WR) is referenced from the rising clock edge at T9. t WR specifies the last burst WRITE cycle until the PRECHARGE command can be issued to the same bank. 3. The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0. 4. DI n = data-in for column n. 5. BC4 (OTF), WL = 5, RL = 5.
DQ INPUT TIMING
Figure 76 shows the strobe to clock timing during a WRITE. DQSx, DQSx\ must transition within 0.25tCK of the clock transitions as limited by tDQSS. All data and data mask setup and hold timings are measured relative to the DQSx, DQSx\ crossings, not the clock crossing. The WRITE preamble and postamble are also shown. One clock prior to data input to the SDRAM, DQSx must be HIGH and DQSx\ must be LOW. Then for a half clock, DQSx is driven LOW (DQSx\ is driven HIGH) during the WRITE preamble. tWPRE, likewise, DQSx must be kept LOW by the memory controller after the last data is written to the SDRAM during the WRITE postamble,tWPST. Data setup and hold times are shown in Figure 86. All setup and hold times are measured from the crossing points of DQSx and DQSx\. These setup and hold values pertain to data input and data mask input. Additionally, the half period of the data input strobe is specified by tDQSH and tDQSL.
FIGURE 86 - DATA INPUT TIMING
DQ S, DQS# t WPRE DQ DM t DS t DQSH DI b t DQSL t WPST
t DH Transitioning Data Don 't Care
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Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
PRECHARGE
Input A10 determines whether one bank or all banks are to be PRECHARGED and in the case where only one bank is to be precharged, inputs BA[2:0] select the array BANK. When all banks are to be PRECHARGED, inputs BA[2:0] are treated as "Don't Care". After a bank is PRECHARGED, it is in the IDLE State and must be ACTIVATED prior to any READ or WRITE commands being issued.
SELF REFRESH
The SELF REFRESH command is initiated like a REFRESH command except CKE is LOW. The DLL is automatically disabled upon entering SELF REFRESH and is automatically enabled and reset upon exiting SELF REFRESH. All power supply inputs (including VREFCA and VREFDQ) must be maintained at valid levels upon entry/exit and during SELF REFRESH mode operation. VREFDQ may float or not drive VccQ/2 while in the SELF REFRESH mode under certain conditions: * VssLOGIC Devices Incorporated
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FIGURE 87 - SELF REFRESH ENTRY/EXIT TIMING
T0 CK# CK
T1
T2
Ta0
Tb0
Tc 0
Tc1
Td0
Te0
Tf0
t CKSRE 1
t CKSRX1
t IS CKE
t CPDED
t IH
t IS Vali d Vali d
t CKESR (MIN)1 t IS ODT2 Vali d
ODTL
RESET# 2
Command
NOP
SRE(REF)3
NOP 4
SRX (NOP)
NOP 5
Vali d 6
Vali d 7
Add ress t RP 8
Vali d
Vali d
t XS 6 , 9 t XSDLL7, 9
Enter self refresh mode (synchronous)
Exit self refresh mode (asynchronous) Indicates a Break in Time Scale Don 't Care
Notes:
1. The clock must be valid and stable meeting t CK specifications at least t CKSRE after entering self refresh mode, and at least t CKSRX prior to exiting self refresh mode, if the clock is stopped or altered between states Ta0 and Tb0. If the clock remains valid and unchanged from entry and during self refresh mode, then t CKSRE and t CKSRX do not apply; however, t CKESR must be satisfied prior to exiting at SRX. 2. ODT must be disabled and RTT off prior to entering self re fresh at state T1. If both R TT_NOM and RTT_WR are disabled in the mode registers, ODT can be a "Don't Care." 3. Self refresh entry (SRE) is synchronous via a REFRESH command with CKE LOW. 4. A NOP or DES command is required at T2 after the SRE command is issued prior to the inputs becoming "Don't Care." 5. NOP or DES commands are required prior to exiting self refresh mode until state Te0. 6. t XS is required before any commands not requiring a locked DLL. 7. t XSDLL is required before any commands requiring a locked DLL. 8. The device must be in the all banks idle state prior to entering self refresh mode. For example, all banks must be precharged, t RP must be met, and no data bursts can be in progress. 9. Self refresh exit is asynchronous; however, t XS and t XSDLL timings start at the first rising clock edge where CKE HIGH satisfies t ISXR at Tc1.t CKSRX timing is also measured so that t ISXR is satisfied at Tc1.
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131
High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
ADVANCE INFORMATION
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
EXTENDED TEMPERATURE USAGE
LOGIC Devices, Inc iMOD DDR3 SDRAM module supports the optional extended temperature range up to 95C while supporting SELF REFRESH/AUTO REFRESH and support Tc temperatures >95C 125C with MANUAL REFRESH only. When using SELF REFRESH/AUTO REFRESH and the case temperature is >85C, SRT and ASR options must be used. The extended range temperature range SDRAM must be REFRESHED externally at 2X anytime the case temperature is >85C. The external REFRESHING requirement is accomplished by reducing the REFRESH PERIOD from 64ms to 32ms. SELF REFRESH mode requires the use of ASR or SRT to support the extended temperature.
TABLE 68: SELF REFRESH TEMPERATURE AND AUTO SELF REFRESH DESCRIPTION
Field MR2 Bits Self Refresh Temperature (SRT)
SRT 7
Description
If ASR is disabled (MR2[6]=0), SRT must be programmed to indicate tOPER during SELF REFRESH; * MR2[7] = 0: Normal operating temperature range (0C to 85C) * MR2[7] = 1: Extended operating temperature range (>85C to 105C) If ASR is enabled (MR2[7]=1), SRT must be set to 0, even if the extended temperature range is supported. *MR2[7]=0: SRT is disabled.
Auto Self Refresh (ASR)
ASR 6 When ASR is enabled, the SDRAM automatically provides SELF REFRESH power management functions, (refresh rate for all supported operating temperature values) *MR2[6]=1: ASR is enabled (M7 must = 0) When ASR is not enabled, the SRT bit must be programmed to indicate tOPER during SELF REFRESH operation. *MR2[6]=0: ASR is disabled, must use manual SELF REFRESH (SRT)
TABLE 69: SELF REFRESH MODE SUMMARY
MR2[6] (ASR)
0 0
MR2[7] (SRT)
0 1
SELF REFRESH Operation
SELF REFRESH Mode is supported in the normal temperature range. SELF REFRESH Mode is supported in normal and extended ( 95C MAX) temperature ranges; When SRT is enabled, it increases self refresh power consumption.
Permitted Operating Temperature Range for Self Refresh Mode
Normal (0C to 85C) Normal and extended (0C to 95C)
1 1
0 1
Self refresh mode is supported in normal and extended temperature ranges; Self refresh power consumption may be temperature-dependent. Illegal.
Normal and extended (0C to 95C)
POWER-DOWN MODE
Power-down is synchronously entered when CKE is registered LOW coincident with a NOP or DES command. CKE is not allowed to go LOW while either an MRS, MPR, ZQCAL, READ or WRITE operation is in progress. CKE is allowed to go LOW while any of the other legal operations are in progress. However, the POWER-DOWN Icc specifications are not applicable until such operations have been completed. Depending on the previous SDRAM state and the command issued prior to CKE going LOW, certain timing constraints must be satisfied (as noted in Table 70). Timing diagrams detailing the different POWER-DOWN mode entry and exits are shown in Figure 88 through Figure 97.
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Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
TABLE 70: COMMAND TO POWER-DOWN ENTRY PARAMETERS
SDRAM Status
Idle or Active Idle or Active Active Active Active Active Active Idle POWER-DOWN Idle
Last Command prior to CKE Low 1
ACTIVATE PRECHARGE READ or READAP WRITE: BL8OTF, BL8MRS, BC4OTF WRITE: BC4MRS WRITEAP: BL8OTF, BL8MRS, BC4OTF WRITEAP: BC4MRS REFRESH REFRESH MODE REGISTER SET
Parameter (MIN)
tACTPDEN tPRPDEN tRDPDEN tWRPDEN tWRAPDEN tREFPDEN tXPDLL tMRSPDEN
Parameter Value
1tCK 1tCK RL = 4tCK + 1tCK WL + 4tCK + tWR/ tCK WL + 2tCK + tWR/ tCK WL + 4tCK + WR + 1tCK WL + 2tCK + WR + 1tCK 1tCK Greater of 10tCK or 24ns
tMOD
Figure
Figure 95 Figure 96 Figure 91 Figure 92 Figure 92 Figure 93 Figure 93 Figure 94 Figure 98 Figure 97
Entering POWER-DOWN mode disables the input and output buffers, excluding CK, CK\, ODT, CKE and RESET\. NOP or DES commands are required until tCPDED has been satisfied, at which time all specified input/output buffers will be disabled. The DLL should be in a locked state when POWER-DOWN is entered for the fastest mode timing. If the DLL is not locked during the POWER-DOWN entry, the DLL must be reset after exiting POWER-DOWN for proper READ operation as well as synchronous ODT operation. During POWER-DOWN entry, if any bank remains open after all in-progress commands are complete, the SDRAM will be in ACTIVE POWER-DOWN. If all banks are closed after all in-progress commands are complete, the SDRAM will be in PRECHARGE POWER-DOWN mode or fast EXIT mode. When entering PRECHARGE POWER-DOWN, the DLL is turned off in slow exit mode or kept on in fast EXIT mode. The DLL remains on when entering ACTIVE POWER-DOWN as well. ODT has special timing constraints when slow EXIT mode, PRECHARGE POWERDOWN is enabled and entered. Refer to "Asynchronous ODT Mode" for detailed ODT usage requirements in slow EXIT mode PRECHARGE POWER-DOWN. A summary of the two POWER-DOWN modes is listed in Table 71. While in either POWER-DOWN state, CKE is held LOW, RESET\ is held HIGH, and a stable clock signal must be maintained. ODT must be in a valid state but all other input signals are a "Don't Care". If RESET\ goes LOW during POWER-DOWN, the SDRAM will switch out of POWER-DOWN and go into the RESET state. After CKE is registered LOW, CKE must remain LOW until tPD (MIN) has been satisfied. The maximum time allowed for POWER-DOWN duration is tPD (MAX) (9 x tREFI). The POWER-DOWN states are synchronously exited when CKE is registered HIGH (with a required NOP or DES command). CKE must be maintained HIGH until tCKE has been satisfied. A valid, executable command may be applied after POWER-DOWN EXIT LATENCY, tXP, tXPDLL have been satisfied. A summary of the POWER-DOWN modes is listed in Table 71.
TABLE 71: POWER-DOWN MODES
SDRAM State
ACTIVE (any bank open) PRECHARGE (all banks PRECHARGED) 0 OFF SLOW
MR1[12]
"Don't Care" 1
DLL State
ON ON
POWER-DOWN exit
FAST FAST
tXP tXP
Relevant Parameters
to any other valid COMMAND to any other valid COMMAND to COMMANDS that require the DLL
tXDLL tXP
to be locked (READ, RDAP, ODT ON). to any other valid COMMAND.
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FIGURE 88 - ACTIVE POWER-DOWN ENTRY AND EXIT
T0 CK# CK t CK
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
t CH
t CL
Command
Valid
NOP t IS
NOP t PD t IH
NOP
NOP
NOP
Valid
CKE
t IH
t IS
t CKE (MIN)
Address
Valid t CPDED Enter power-down mode Exit power-down mode Indicates a Break in Time Scale t XP
Valid
Don't Care
FIGURE 89 - PRECHARGE POWER-DOWN (FAST-EXIT MODE) ENTRY AND EXIT
T0 CK# CK t CK
T1
T2
T3
T4
T5
Ta0
Ta1
t CH NOP
t CL NOP NOP NOP NOP Valid
Co m m an d
t CPDED
t CKE (MIN)
t IS CKE
t IH
tCKEmin
t IS
tCKEmin
t PD Enter power-down mode
t XP Exit power-down mode Indicates a Break in Time Scale Don't Care
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Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FIGURE 90 - PRECHARGE POWER-DOWN (SLOW-EXIT MODE) ENTRY AND EXIT
T0 CK# CK t CK PRE
T1
T2
T3
T4
Ta
Ta1
Tb
t CH NOP
t CL NOP NOP NOP Valid 1 Valid 2
Command
t CPDED
t CKE (MIN) t XP
t IS CKE t PD Enter power-down mode
t IH t IS t XPDLL
Exit power-down mode Indicates a Break in Time Scale Don't Care
Notes:
1. Any valid command not requiring a locked DLL. 2. Any valid command requiring a locked DLL.
FIGURE 91 - POWER-DOWN ENTRY AFTER READ OR READ WITH AUTO PRECHARGE (RDAP)
CK# CK
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Ta8
Ta9
Ta10
Ta11
Ta12
Command
READ/ RDAP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP t IS t CPDED
NOP
CKE
Add ress
Vali d RL = AL + CL t PD
DQS, DQS#
DQ BL8
DI n
DI DI n+1 n+2
DI n+3
DI n+4
DI n+ 5
DI n+6
DI n+7
DQ BC4
DI n
DI n+1
DI n+2
DI n+3
t RDPDEN
Power- down or self refresh entry
Indicates a Break In Time Sc ale
Transitionin g Data
Don 't Care
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2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FIGURE 92 - POWER-DOWN ENTRY AFTER WRITE
CK# CK
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Tb0
Tb1
Tb2
Tb3
Tb4
Command
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP t IS t CPDED
NOP
CKE
Add ress
Valid WL = AL + CWL t WR t PD
DQS, DQS#
DQ BL8
DI n
DI DI n+1 n+2
DI n+3
DI n+4
DI n+5
DI n+6
DI n+7
DQ BC4
DI n
DI n+1
DI n+2
DI n+3
t WRPDEN Power- down or self refresh entry 1
Indicates A Break in Time Scale
Transitioning Data
Don 't Care
Notes:
1. CKE can go LOW 2 tCK earlier if BC4MRS.
FIGURE 93 - POWER-DOWN ENTRY AFTER WRITE WITH AUTO PRECHARGE (WRAP)
CK# CK T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb0 Tb1 Tb2 Tb3 Tb4
Command
WRAP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
t IS CKE
t CPDED
Add ress
Vali d
A10 WL = AL + CWL DQS, DQS# WR1 t PD
DQ BL8
DI n
DI n+1
DI n+2
DI DI n+3 n+4
DI n+5
DI n+6
DI n+7
DQ BC4
DI n
DI n+1
DI n+2
DI n+3
t WRAPDEN Start internal pre char ge Power- down or self refresh entry 2 Indicates a Break in Time Scale
Transitioning Data
Don 't Care
Notes:
1.
is programmed through MR0[11:9] and represents t WR (MIN)ns/ t CK rounded up to the next integer t CK. 2. CKE can go LOW 2 tCK earlier if BC4MRS.
t WR
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2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FIGURE 94 - REFRESH TO POWER-DOWN ENTRY
T0 CK# CK t CK
T1
T2
T3
Ta0
Ta1
Ta2
Tb0
t CH
t CL
Command
REFRESH
NOP t CPDED t IS
NOP
NOP
NOP
Valid
t CKE (MIN) t PD
CKE t REFPDEN t RFC (MIN)1 t XP (MIN)
Indicates a Break In Time Scale
Don't Care
Notes:
1. After CKE goes HIGH during t RFC, CKE must remain HIGH until t RFC is satisfied.
FIGURE 95 - ACTIVATE TO POWER-DOWN ENTRY
T0 CK# CK t CK
T1
T2
T3
T4
T5
T6
T7
t CH
t CL
Command
ACTIVE
NOP
NOP
Address
Valid t CPDED t IS t PD
CKE t ACTPDEN
tCKE
Don't Care
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FIGURE 96 - PRECHARGE TO POWER-DOWN ENTRY
T0 CK# CK t CK
T1
T2
T3
T4
T5
T6
T7
t CH
t CL
Command
PRE
NOP
NOP
Address
All/single bank
t CPDED t IS CKE t PREPDEN t PD
Don't Care
FIGURE 97 - MRS COMMAND TO POWER-DOWN ENTRY
T0 CK# CK t CK
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
t CH
t CL
t CPDED
Command
MRS
NOP
NOP
NOP
NOP
NOP
Address
Valid t MRSPDEN t IS t PD
CKE
Indicates a Break in Time Scale
Don't Care
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FIGURE 98 - POWER-DOWN EXIT TO REFRESH TO POWER-DOWN ENTRY
T0 CK# CK t CK t CH t CL T1 T2 T3 T4 Ta0 Ta1 Tb0
Command
NOP
NOP
NOP
NOP
REFRESH
NOP
NOP
t CPDED
t XP1
t IS CKE t PD Enter power-down mode
t IH t IS t XPDLL 2 Exit power-down mode Enter power-down mode
Indicates a Break in Time Scale
Don't Care
Notes:
1. t XP must be satisfied before issuing the command. 2. t XPDLL must be satisfied (referenced to the registration of power-down exit) before the next power-down can be entered.
RESET
The RESET signal (RESET\) is an asynchronous signal that triggers any time it drops LOW and there are no restrictions about when it can go LOW. After RESET\ is driven LOW, it must remain LOW for 100ns. During this time, the outputs are disabled, ODT (RTT) turns off (HIGH-Z) and the DDR3 SDRAM resets itself. CKE should be brought LOW prior to RESET\ being driven HIGH. After RESET\ goes HIGH, the SDRAM must be re-initialized as though a normal power up were executed (see Figure 99). All refresh counters on the SDRAM are RESET and data stored in the SDRAM is assumed unknown after RESET\ has been driven LOW.
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FIGURE 99 - RESET SEQUENCE
System RESET (warm boot) Sta ble an d vali d clo ck CK# CK T (MIN) = MAX (10ns, 5 t CK) T = 100ns (MIN) RESET# t IOZ t IS Vali d t CL t CL
T0
T1 t CK
Ta0
Tb0
Tc0
Td0
T=10ns (MIN) CKE
ODT t IS Command NOP MRS MRS
Vali d
Vali d
Vali d
Vali d
MRS
MRS
ZQ CL
Vali d
DM
Add ress
Code
Code
Code
Code
Vali d
A10
Code
Code
Code
Code
A10 = H
Vali d
BA[2:0]
BA0 = L BA1 = H BA2 = L High-Z
BA0 = H BA1 = H BA2 = L
BA0 = H BA1 = L BA2 = L
BA0 = L BA1 = L BA2 = L
Vali d
DQS DQ
High-Z
RTT
High-Z
T = 500s (MIN)
t XPR
t MRD
t MRD
t MRD
t MOD
MR2 All voltage supplies valid and stable DRAM rea dy for external commands
MR3
MR1 with DLL ENABLE
MR0 with DLL RESET
ZQ CAL t ZQ INIT t DLLK
Normal operation Indicates a Break in Time Scale Don 't Care
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
ON-DIE TERMINATION (ODT)
ODT is a feature that enables the SDRAM to enable/disable on-die termination resistance for each DQ, LDQSx, LDQSx\ , UDQSx, UDQSx\ LDMx and UDMx for the four words contained in LDI's DDR3 iMOD. The ODT feature is designed to improve signal integrity of the memory array/ sub-system by enabling the DDR3 memory controller to independently turn on or off the SDRAMS internal termination resistance for any grouping of SDRAM devices. The ODT feature is not supported during DLL disable mode. A simple functional representation of the SDRAM ODT feature is shown in Figure 100. The switch is enabled by the internal ODT control logic, which uses the external ODT ball and other control information.
FUNCTIONAL REPRESENTATION OF ODT
The value of RTT (ODT termination value) is determined by the settings of several mode register bits (see Table 75). The ODT ball is ignored while in SELF REFRESH mode (must be turned off prior to SELF REFRESH entry) or if mode registers MR1 and MR2 are programmed to disable ODT. ODT is comprised of nominal ODT and dynamic ODT modes and either of these can function in synchronous or asynchronous modes (when the DLL is off during PRECHARGE POWER-DOWN or when the DLL is synchronizing). Nominal ODT is the base termination and is used in any allowable ODT state. Dynamic ODT is applied only during WRITEs and provides OTF switching from no RTT or RTT_NOM to RTT_WR. The actual effective termination, RTT_EFF may be different from the RTT targeted due to nonlinearity of the termination. For RTT_EFF values and calculations, see "ODT Characteristics".
FIGURE 100 - ON-DIE TERMINATION
NOMINAL ODT
ODT (NOM) is the base termination resistance for each applicable ball, enabled or disabled via MR1[9,6,2] (see Figure 46), and it is turned on or off via the ODT ball.
ODT To other circuitry such as RCV, ... VCCQ/2 RTT Switch DQ, DQS, DQS#, DM
TABLE 72: POWER-DOWN MODES
MR1[9,6,2]
000 000 000-101 000-101 110 and 111
ODT Pin
0 1 0 1 X
SDRAM Termination State
RTT_NOM disabled, ODT OFF RTT_NOM disabled, ODT ON RTT_NOM enabled, ODT OFF RTT_NOM enabled, ODT ON RTT_NOM reserved, ODT ON or OFF
SDRAM State
Any valid Any valid except SELF REFRESH, READ Any valid Any valid except SELF REFRESH, READ Illegal
Notes
1,2 1,3 1,2 1,3
NOTES: 1. 2. Assumes dynamic ODT is disabled. ODT is enabled and active during most WRITES for proper termination, but it is not illegal to have it off during WRITES. 3. ODT must be disabled during READs. The RTT_NOM value is restricted during WRITES. Dynamic ODT is applicable if enabled.
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High Performance, Integrated Memory Module Product
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
NOMINAL ODT
Nominal ODT resistance RTT_NOM is defined by MR1[9,6,2], as shown in Figure 46. The RTT_NOM termination value applies to the output pins previously mentioned. DDR3 SDRAM iMODs support multiple RTT_NOM values based on RZQ/n where n can be 2,4,6,8 or 12 and RZQ is 2401%. RTT_NOM termination is allowed any time after the SDRAM is initialized, calibrated and not performing READ accesses or when it is not in SELF REFRESH mode. WRITE access uses RTT_NOM id dynamic ODT (RTT_WR) is disabled. If RTT_NOM is used during WRITEs, only RZQ/2, RZQ/4 and RZQ/6 are allowed (see Table 71). ODT timings are summarized in Table 73, as well as, listed in Table 50. Examples of nominal ODT timing are shown in conjunction with the synchronous mode of operation in "Synchronous ODT Mode".
TABLE 73: ODT PARAMETER
Symbol
ODTL ON ODTL OFF
tAONPD tAOFFPD
Description
ODT synchronous turn on delay ODT synchronous turn off delay ODT asynchronous on delay ODT asynchronous on delay ODT minimum HIGH time after ODT assertion or WRITE (BC4)
Begins at
ODT registered HIGH ODT registered HIGH ODT registered HIGH ODT registered HIGH ODT registered HIGH or WRITE registration with ODT HIGH WRITE registration with ODT HIGH Completion of ODTL on Completion of ODTL off
Defined to
RTT_ON tAON RTT_ON tAOF RTT_ON RTT_OFF ODT registered LOW
Definition for All DDR3 bins
CWL + AL - 2 CWL + AL - 2 1-9 1-9 4TcK
Units
tCK tCK
ns ns
tCK
ODTH4
ODTH8
tAON tAOF
ODT minimum HIGH time after WRITE (BL8) ODT turn-on relative to ODTL on completion ODT turn-off relative to ODTL off completion
ODT registered LOW RTT_ON RTT_OFF
6TcK See Table 50 0.5TcK 0.2TcK
tCK
ps
tCK
DYNAMIC ODT
In certain applications, to further enhance signal integrity on the data bus, it is desirable that the termination strength, be changed without issuing an MRS command, essentially changing the ODT termination resistance on-the-fly. With dynamic ODT (RTT_WR) enabled, the SDRAM switches from nominal ODT (RTT_NOM) to dynamic ODT when beginning a WRITE burst and subsequently switches back to nominal ODT at the completion of the WRITE burst sequence. This requirement and the supporting DYNAMIC ODT feature of the DDR3 SDRAM makes it feasible and is described in further detail below:
DYNAMIC ODT FUNCTIONAL DESCRIPTION:
The dynamic ODT mode is enabled if either MR2[9] or mR2[10] is set to "1". Dynamic ODT is not supported during DLL disable mode, so RTT_WR must be disabled. The dynamic ODT function is described, as follows: * Two RTT values are available - RTT_NOM and RTT_WR: * The value of RTT_NOM is preselected via MR1[9,6,2] * The value for RTT_WR is preselected via MR2[10,9] * During SDRAM operations without READ or WRITE commands, the termination is controlled as follows: * Termination ON/OFF timing is controlled via the ODT ball and LATENCIES ODTl on and ODTL off * Nominal termination strength RTT_NOM is used * When a WRITE command (WR, WRAP, WRS4, WRS8, WRAPS4, WRAPS8) is registered and if dynamic ODT is enabled, the ODT termination is controlled as follows: * A latency of ODTLCNW after the WRITE command: termination strength RTT_NOM switches to RTT_WR * A Latency of ODTLCWN8 (for BL8, fixed or OTF) or ODTLCWN4 (for BC4, fixed or OTF) after the WRITE command: termination strength RTT_WR switches back to RTT_NOM * ON/OFF termination timing is controlled via the ODT ball and determined by ODTL on, ODTL off, ODTH4 and ODTH8. * During the tADC transition window, the value of RTT is undefined ODT is constrained during WRITEs and when dynamic ODT is enabled (see Table 74).
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High Performance, Integrated Memory Module Product
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
TABLE 74: DYNAMIC ODT SPECIFIC PARAMETERS
Symbol
ODTLCNW ODTLCWN4 ODTLCWN8
tADC
Description
Change from RTT_NOM to RTT_WR Change from RTT_WR to RTT_NOM (BC4) Change from RTT_WR to RTT_NOM (BL8) RTT change skew
Begins at
WRITE registration WRITE registration WRITE registration ODTLCNW
Defined to
RTT switched from RTT_NOM to RTT_WR RTT switched from RTT_WR to RTT_NOM RTT switched from RTT_WR to RTT_NOM RTT trans complete
Definition for All DDR3 bins
WL - 2 4tCK + ODTL OFF 6tCK + ODTL OFF
Units
tCK tCK tCK tCK
0.5tCK 0.2tCK
TABLE 75: MODE REGISTERS FOR RTT_NOM
M9
0 0 0 0 1 1 1 1
MR1(RTT_NOM) M6
0 0 1 1 0 0 1 1
M2
0 1 0 1 0 1 0 1
RTT_NOM (RZQ)
Off RZQ/4 RZQ/2 RZQ/6 RZQ/12 RZQ/8 Reserved Reserved
RTT_NOM(Ohms)
Off 60 120 40 20 30 Reserved Reserved
RTT_NOM Mode Restriction
n/a SELF REFRESH
SELF REFRESH, WRITE
n/a n/a
TABLE 76: MODE REGISTERS FOR RTT_WR
MR1(RTT_NOM) M10
0 0 1 1 n/a n/a n/a n/a
M2
0 1 0 1 n/a n/a n/a n/a
RTT_NOM (RZQ)
RZQ/4 RZQ/2 Reserved n/a n/a n/a n/a
RTT_NOM(Ohms)
60 120 Reserved n/a n/a n/a n/a
Dynamic ODT OFF: WRITE does not affect RTT_NOM
TABLE 77: TIMING DIAGRAMS FOR DYNAMIC ODT
Figure
Figure 101 Figure 102 Figure 103 Figure 104 Figure 105
Title
Dynamic ODT: ODT asserted before and after the WRITE, BC4 Dynamic ODT: Without WRITE command Dynamic ODT: ODT pin asserted together with WRITE command for 6 CK cycles, BL8 Dynamic ODT: ODT pin asserted with WRITE command for 6 CK cycles, BC4 Dynamic ODT: ODT pin asserted with WRITE command for 4 CK cycles, BC4
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High Performance, Integrated Memory Module Product
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FIGURE 101 - DYNAMIC ODT: ODT ASSERTED BEFORE AND AFTER THE WRITE, BC4
T0 CK# CK Command Add ress NOP
T1
T2
T3
T4
T5
T 6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
NOP
NOP
NOP
WRS4 Vali d
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ODTH4 ODTH4 ODT ODTL on t AON (MIN) RTT RTT_NOM t AON (MAX) ODTLCNW DQS, DQS# DQ WL
DI n DI n +1 DI n +2 DI n +3
ODTL off
ODTLCWN4 t ADC (MIN) RTT_WR t ADC (MAX) t ADC (MAX) t ADC (MIN) RTT_NOM t AOF (MAX) t AOF (MIN)
Transitioning
Don 't Care
Notes:
1. Via MRS or OTF. AL = 0, CWL = 5. RTT_NOM and RTT_WR are enabled. 2. ODTH4 applies to first registering ODT HIGH and then to the registration of the WRITE command. In this example, ODTH4 is satisfied if ODT goes LOW at T8 (four clocks after the WRITE command).
FIGURE 102 - DYNAMIC ODT: WITHOUT WRITE COMMAND
CK# CK Command Add ress
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
Vali d
Vali d
Vali d
Vali d
Vali d
Vali d
Vali d
Vali d
Vali d
Vali d
Vali d
Vali d
ODTH4 ODTL on ODT t AON (MAX) RTT t AON (MIN) DQS, DQS# DQ RTT_NOM
ODTL off
t AOF (MIN) t AOF (MAX)
Transitionin g
Don 't Care
Notes:
1. AL = 0, CWL = 5. RTT_NOM is enabled and R TT_WR is either enabled or disabled. 2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW; in this example, ODTH4 is satisfied. ODT registered LOW at T5 is also legal.
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FIGURE 103 - DYNAMIC ODT: ODT PIN ASSERTED TOGETHER WITH WRITE COMMAND FOR 6 CLOCK CYCLES, BL8
T0 CK# CK Command NOP
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
WRS8
NOP ODTLCNW
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Add ress
Vali d ODTH8 ODTLON ODTLOFF
ODT t ADC (MAX) RTT t AON (MIN) ODTLCWN8 t AOF (MAX) RTT_WR t AOF (MIN)
DQS, DQS# WL
DQ
DI b
DI b+1
DI b+2
DI b+3
DI b+4
DI b+5
DI b+6
DI b+7
Transitioning
Don 't Care
Notes:
1. Via MRS or OTF; AL = 0, CWL = 5. If RTT_NOM can be either enabled or disabled, ODT can be HIGH. RTT_WR is enabled. 2. In this example, ODTH8 = 6 is satisfied exactly.
FIGURE 104 - DYNAMIC ODT: ODT PIN ASSERTED WITH WRITE COMMAND FOR 6 CLOCK CYCLES, BC4
T0 CK# CK Command NOP WRS4 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
ODTLCNW
Address Vali d ODTH4 ODT ODTL on t ADC (MAX) RTT t AON (MIN) ODTLCWN4 DQS, DQS# DQ WL Transitioning Don 't Care
DI n DI n+1 DI n+2 DI n+3
ODTL off
t ADC (MIN) RTT_WR RTT_NOM t ADC (MAX)
t AOF (MIN) t AOF (MAX)
Notes:
1. Via MRS or OTF. AL = 0, CWL = 5. RTT_NOM and RTT_WR are enabled. 2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW, so in this example, ODTH4 is satisfied. ODT registered LOW at T5 is also legal.
LOGIC Devices Incorporated
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145
High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
ADVANCE INFORMATION
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FIGURE 105 - DYNAMIC ODT: ODT PIN ASSERTED WITH WRITE COMMAND FOR 4 CLOCK CYCLES, BC4
T0 CK# CK Command NOP WRS4 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
ODTLCNW Add ress Valid ODTH4 ODT ODTL on RTT t AON (MIN) ODTLCWN4 DQS, DQS# WL DQ
DI n DI n+1 DI n+2 DI n+3
ODTL off
t ADC (MAX) RTT_WR RTT_WR
t AOF (MIN)
t AOF (MAX)
Transitioning
Don 't Care
Notes:
1. Via MRS or OTF. AL = 0, CWL = 5. RTT_NOM can be either enabled or disabled. If disabled, ODT can remain HIGH. RTT_WR is enabled. 2. In this example ODTH4 = 4 is satisfied exactly.
SYNCHRONOUS ODT MODE
Synchronous ODT is selected whenever the DLL is turned on and locked while RTT_NOM or RTT_WR is enabled. Based on the POWER-DOWN definition, these modes are: * Any bank ACTIVE with CKE HIGH * REFRESH mode with CKE HIGH * DLE mode with CKE HIGH * ACTIVE POWER-DOWN mode (regardless of MR0[12]) * PRECHARGE POWER-DOWN mode if DLL is enabled during PRECHARGE POWER-DOWN by MR0[12]
ODT LATENCY AND POSTED ODT
In synchronous ODT mode, RTT turns on ODTL on clock cycles after ODT is sampled HIGH by a rising clock edge and turns off ODTL off clock cycles after ODT is registered LOW by a rising clock edge. The actual on/off times varies by tAON and tAOF around each clock edge (see Table 78). The ODT LATENCY is tied to the WRITE LATENCY (WL) by ODTL on =WL-2 and ODTL off = WL- 2. Since WRITE LATENCY is made up of CAS WRITE LATENCY (CWL) and ADDITIVE LATENCY (AL), the AL value programmed into the mode register MR1[4,3], also applies to the ODT signal. The SDRAM's internal ODT signal is delayed a number of clock cycles defined by the AL relative to the external ODT signal. Thus, ODTL on = CWL + AL - 2 and ODTL off = CWL + AL - 2.
LOGIC Devices Incorporated
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146
High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
ADVANCE INFORMATION
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
SYNCHRONOUS ODT TIMING PARAMETERS
Synchronous ODT mode uses the following timing parameters: ODTL on, ODTL off, ODTH4, ODTH8, tAON and tAOF (see Table 78 and Figure 106). The minimum RTT turn-on time (tAON [MIN]) is the point at which the device leaves HIGH-A and ODT resistance begins to turn on. Maximum RTT turn-on time (tAON [MAX]) is the point at which ODT resistance is fully on. Both are measured relative to ODTL on. The minimum RTT turn-off time (tAOF [min]) is the point at which the device starts to turn-off ODT resistance. Maximum RTT turn-off time (tAOF [MAX]) is the point at which ODT has reached HIGH-Z. Both are measured from ODTL off. When ODT is asserted, it must remain HIGH until ODTH4 is satisfied. If a WRITE command is registered by the SDRAM with ODT HIGH, then ODT must remain HIGH until ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (see Figure 107). ODTH4 and ODTH8 are measured from ODT registered HIGH to ODT registered LOW or from the registration of a WRITE command until ODT is registered LOW.
TABLE 78: SYNCHRONOUS ODT PARAMETERS
Symbol
ODTL ON ODTL OFF ODTH4
Description
ODT synchronous TURN-ON delay ODT synchronous TURN-OFF delay ODT Minimum HIGH time after ODT assertion or WRITE (BC4)
Begins at
ODT registered HIGH ODT registered HIGH ODT registered HIGH, or WRITE registration with ODT HIGH WRITE registration with ODT HIGH
Defined to
RTT_ON tAON RTT_OFF tAOF ODT registered LOW
Definition for All DDR3 bins
CWL + AL - 2 CWL + AL - 2 4tcK
Units
tCK tCK tCK
ODTH8
ODT Minimum HIGH time after WRITE (BL8)
ODT registered LOW
6tcK
tCK
tAON
ODT TURN-ON relative to ODTL on completion
Completion of ODTL on
RTT_ON
See Table 50
ps
tAOF
ODT TURN-OFF relative to ODTL off completion
Completion of ODTL off
RTT_OFF
0.5tcK 0.2tcK
tCK
FIGURE 106 - SYNCHRONOUS ODT
T0 CK# CK CKE
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
AL = 3
AL = 3
CWL -
ODT ODTH4 (MIN) ODTL off = CWL + AL - 2
ODTL on = CWL + AL - 2 t AON (MIN) RTT t AON (MAX) RTT_NOM
Notes:
1. AL = 3; CWL = 5; ODTL on = WL = 6.0; ODTL off = WL - 2 = 6. R TT_NOM is enabled.
LOGIC Devices Incorporated
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147
High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
ADVANCE INFORMATION
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FIGURE 107 - SYNCHRONOUS ODT (BC4)
T0 CK# CK CKE Command NOP NOP NOP NOP ODTH4 NOP NOP NOP WRS4 NOP ODTH4 (MIN) ODTH4 ODT ODTL off = WL - 2 ODTL on = WL - 2 t AON (MIN) RTT t AON (MAX) RTT_NOM t AOF (MAX) t AON (MIN) ODTL on = WL - 2 t AOF (MIN) t AON (MAX) RTT_NOM t AOF (MAX) t AOF (MIN) ODTLoff = WL - 2 NOP NOP NOP NOP NOP NOP NOP NOP NOP T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17
Transitioning
Don 't Care
Notes:
1. 2. 3. 4.
WL = 7. RTT_NOM is enabled. RTT_WR is disabled. ODT must be held HIGH for at least ODTH4 after assertion (T1). ODT must be kept HIGH ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (T7). ODTH is measured from ODT first registered HIGH to ODT first registered LOW or from the registration of the WRITE command with ODT HIGH to ODT registered LOW. 5. Although ODTH4 is satisfied from ODT registered HIGH at T6, ODT must not go LOW before T11 as ODTH4 must also be satisfied from the registration of the WRITE command at T7.
ODT OFF DURING READS
As the DDR3 SDRAM cannot terminate and drive at the same time, RTT must be disabled at least one-half clock cycle before the READ preamble by driving the ODT ball LOW. RTT may not be enabled until the end of the postamble as shown in Figure 108.
FIGURE 108 - ODT DURING READS
T0 CK# CK Command Add ress READ Vali d
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ODTL on = CWL + AL - 2 ODTL off = CWL + AL - 2 ODT t AOF (MIN) RTT RTT_NOM RL = AL + CL DQS, DQS# DQ
DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7
RTT_NOM t AOF (MAX) t AON (MAX)
Transitioning
Don 't Care
Notes:
1. ODT must be disabled externally during READs by driving ODT LOW. For example, CL = 6; AL = CL - 1 = 5; RL = AL + CL = 11; CWL = 5; ODTL on = CWL + AL - 2 = 8; ODTL off = CWL + AL - 2 = 8. RTT_NOM is enabled. RTT_WR is a "Don't Care."
LOGIC Devices Incorporated
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148
High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
ADVANCE INFORMATION
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
ASYNCHRONOUS ODT MODE
Asynchronous ODT mode is available when the SDRAM runs in DLL ON mode and when either RTT_NOM or RTT_WR is enabled; however, the DLL is temporarily turned off in PRECHARGED POWER-DOWN standby via MR0[12]. Additionally, ODT operates asynchronously when the DLL is synchronizing after being RESET. See "POWER-DOWN MODE" for definition and guidance over POWER-DOWN details. In asynchronous ODT timing mode, the internal ODT command is not delayed by AL relative to the external ODT command. In asynchronous ODT mode, ODT controls RTT by analog time. The timing parameters tAONPD and tAOFPD (see Table 79) replace ODTL on/tAON and ODTL off/tAOF respectively, when ODT operates asynchronously (see Figure 109). The minimum RTT turn-on time (tAONPD [MIN]) is the point at which the device termination circuit leaves HIGH-Z and ODT resistance begins to turn-on. Maximum RTT turn-on time (tAONPD [MAX]) is the point at which ODT resistance is fully on. tAONPD (MIN) and tAONPD (MAX) are measured from ODT being sampled HIGH. The minimum RTT turn-off time (tAOFPD [MIN]) is the point at which the device termination circuit starts to turn off ODT resistance. Maximum RTT turn-off time (tAOFPD [MAX]) is the point at which ODT has reached HIGH-Z. tAOFPD (MIN) and tAOFPD (MAX) are measured from ODT being sampled LOW.
FIGURE 109 - ASYNCHRONOUS ODT TIMING WITH FAST ODT TRANSITION
T0 CK# CK CKE
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
t IH ODT
t IS
t IH
t IS
t AONPD (MIN) RTT t AONPD (MAX) RTT_NOM
t AOFPD (MIN)
t AOFPD (MAX) Transitioning Don 't Care
Notes:
1. AL is ignored.
TABLE 79: ASYNCHRONOUS ODT TIMING PARAMETERS FOR ALL SPEED BINS
Symbol
tAON PD tAOF PD
Description
Asynchronous RTT TURN-ON delay (POWER-DOWN with DLL off) Asynchronous RTT TURN-OFF delay (POWER-DOWN with DLL off)
MIN
2 2
MAX
8.5 8.5
Units
ns ns
LOGIC Devices Incorporated
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149
High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
SYNCHRONOUS TO ASYNCHRONOUS ODT MODE TRANSITION (POWER-DOWN ENTRY)
There is a transition period around POWER-DOWN ENTRY (PDE) where the SDRAM's ODT may exhibit either synchronous or asynchronous behavior. This transition period occurs if the DLL is selected to be off when in PRECHARGE POWER-DOWN mode by the setting of MR0[12] = 0. POWER-DOWN entry begins tANPD prior to CKE first being registered LOW and it ends when CLE is first registered LOW. tANPD is equal to the greater of ODTL off + 1tCK or ODTL on + 1tCK. If a REFRESH command has been issued, and it is in progress when CKE goes LOW, POWER-DOWN entry will end tRFC after the REFRESH command rather than when CKE is first registered LOW. POWER-DOWN ENTRY will then become the greater of tANPD and tRFC - REFRESH command to CKE registered LOW. ODT assertion during POWER-DOWN ENTRY results in an RTT change as early as the lesser of tAONPD (MIN) and ODTL on x tCK + tAON (MIN) or as late as the greater of tAONPD (MAX) and ODTL on x tCK + tAON (MAX). ODT de-assertion during POWER-DOWN ENTRY may result in an RTT change as early as the lesser of tAOFPD (MIN) and ODTL off x tCK + tAOF (MIN) or as late as the greater of tAOFPD (MAX) and ODTL off x tCK + tAOF (MAX). Table 80 summarizes these parameters. If the AL has a large value, the uncertainty of the state of RTT becomes quite large. This is because ODTL on and ODTL off are derived from the WL and WL is equal to CWL + AL. Figure 110 shows three different cases; * ODT_A: Synchronous behavior before tANPD * ODT_B: ODT state changes during the transition period with tAONPD (MIN) less than ODTL on x tCK + tAON (MIN) and tAONPD (MAX) greater than ODTL on x tCK + tAON (MAX) * ODT_C: ODT state changes after the transition period with asynchronous behavior
TABLE 80: ODT PARAMETERS FOR POWER-DOWN (DLL OFF) ENTRY AND EXIT TRANSITION PERIOD
Description
POWER-DOWN entry transition period (POWER-DOWN entry) POWER-DOWN entry transition (POWER-DOWN exit) ODT to RTT TURN-ON delay (ODTL on = WL - 2)
MIN
tAN tXPDLL
MAX
Greater of: tANPD or tRFC - REFRESH to CKE LOW
PD +
Lesser of: tANPD (MIN) [1ns] or ODL on x tCK + tAON (MIN) Lesser of: tAOFPD (MIN) [1ns] or ODL off x tCK + tAOF (MIN)
Lesser of: tANPD (MIN) [1ns] or ODL on x tCK + tAON (MIN) Lesser of: tAOFPD (MIN) [1ns] or ODL off x tCK + tAOF (MIN)
ODT to RTT TURN-OFF delay (ODTL off = WL - 2)
tAN
PD
WL - 1 (Greater of ODTL off + 1 or ODTL on + 1)
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L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FIGURE 110 - SYNCHRONOUS TO ASYNCHRONOUS TRANSITION DURING PRECHARGE POWER-DOWN (DLL OFF) ENTRY
T0 CK# CK CKE Command NOP REF NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 Ta0 Ta1 Ta2 Ta3
t RFC (MIN) t ANPD PDE transition period ODT A synchronous DRAM RTT A synchronous RTT_NOM ODTL off t AOF (MAX)
t AOF (MIN) ODTL off + t AOFPD (MIN) t AOFPD (MAX)
ODT B asynchronous or synchronous DRAM RTT B asynchronous or synchronous ODT C asynchronous RTT_NOM
t AOFPD (MIN) ODTL off + t AOFPD (MAX)
t AOFPD (MIN) DRAM RTT C asynchronous RTT_NOM t AOFPD (MAX)
Indicates a Break In Time Scale
Transitioning
Don 't Care
Notes:
1. AL = 0; CWL = 5; ODTL off = WL - 2 = 3.
ASYNCHRONOUS TO SYNCHRONOUS ODT MODE TRANSITION (POWER-DOWN EXIT)
The SDRAM's ODT may exhibit either asynchronous or synchronous behavior during POWER-DOWN EXIT (PDX). This transition period occurs if the DLL is selected to be off when in PRECHARGE POWER-DOWN mode by setting MR0[12] to "0". POWER-DOWN exit begins tANPD prior to CKE first being registered HIGH and it ends tXPDLL after CKE is first registered HIGH. tANPD is equal to the greater of ODTL off + 1tCK or ODTL on + 1tCK. The transition period is tANPD plus tXPDLL. ODT assertion during POWER-DOWN exit results in an RTT change as early as the lesser of tAONPD (MIN) and ODTL on x tCK + tAON (MIN) or as late as the greater of tAONPD (MAX) and ODTL on x tCK + tAON (MAX). ODT de-assertion during POWER-DOWN EXIT may result in an RTT change as early as the lesser of tAOFPD (MIN) and OFTL off x tCK + tAOF (MIN) or as late as the greater of tAOFPD (MAX) and ODTL off x tCK + tAOF (MAX). Table 80 summarizes these parameters. If the AL has a large value, the uncertainty of the RTT state becomes quite large. This is because ODTL on and ODTL off are derived from the WL, and the WL is equal to CWL + AL. Figure 111 shows three different cases. * ODT C: Asynchronous behavior before tANPD * ODT B: ODT state changes during the transition period with tAOFPD (MIN) less than ODTL off x tCK + tAOF (MIN) and ODTL off x tCK + tAOF (MAX) greater than tAOFPD (MAX) * ODT A: ODT state changes after the transition period with synchronous response
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151
High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
High Performance, Integrated Memory Module Product
Ta3 Ta4 Ta5 Ta 6 T b0 Tb1 Tb2 Tc0 NOP NOP NOP NOP t XPDLL PDX transition period NOP NOP NOP NOP ODTL off + t AOF (MIN) t AOFPD (MAX) t AOFPD (MIN) ODTL off + t AOF (MAX) RTT_NOM
FIGURE 111 - ASYNCHRONOUS TO SYNCHRONOUS TRANSITION DURING PRECHARGE POWER-DOWN (DLL OFF) EXIT
ADVANCE INFORMATION
T0 CK# CK CKE COMMAND NOP t ANPD NOP
T1
T2
Ta0
Ta1
Ta2
Tc1
Tc2
Td0
Td1
NOP
NOP
NOP
NOP
ODT A asynchronous DRAM RTT A asynchronous RTT_NOM t AOFPD (MAX) ODT B asynchronous or synchronous RTT B asynchronous or synchronous RTT_NOM t AOFPD (MIN)
ODTL off
t AOF (MAX)
ODT C synchronous DRAM RTT C synchronous
t AOF (MIN)
Indicates A Break in Time Scale
Transitioning
Don 't Care
Notes:
1. CL = 6; AL = CL - 1; CWL = 5; ODTL off = WL - 2 = 8.
LOGIC Devices Incorporated
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Jul 08, 2009 LDS-L9D320G32BG6-A
L9D320G32BG6
ADVANCE INFORMATION
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
ASYNCHRONOUS TO SYNCHRONOUS ODT MODE TRANSITION (SHORT CKE PULSE)
If the time in the PRECHARGE POWER DOWN or IDLE states is very short (short CKE LOW pules), the POWER-DOWN ENTRY and POWER-DOWN EXIT transition periods will overlap. When overlap occurs, the response of the SDRAM's RTT to a change in the ODT state may be synchronous or asynchronous from the start of the POWER-DOWN ENTRY transition period to the end of the POWER-DOWN EXIT transition period even if the ENTRY period ends later than the EXIT period. (see Figure 112). If the time in the idle state is very short (short CKE HIGH pulse), the POWER-DOWN EXIT and POWER-DOWN ENTRY transition periods overlap. When this overlap occurs, the response of the SDRAM's RTT to a change in the ODT state may be synchronous or asynchronous from the start of the POWER-DOWN EXIT transition period to the end of the POWER-DOWN ENTRY transition period (see Figure 113).
FIGURE 112 - TRANSITION PERIOD FOR SHORT CKE LOW CYCLES WITH ENTRY AND EXIT PERIOD OVERLAPPING
T0 CK# CK Command CKE PDE transition period t ANPD t RFC(MIN) PDX transition perio d t ANPD Short CKE LOW transition period (RTT chan ge asynchronous or syn chronous) t XPDLL REF NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP T1 T2 T3 T4 T5 T6 T7 T8 T9 Ta0 Ta1 Ta2 Ta3 Ta4
Indicates a Break in Time Scale
Transitionin g
Don 't Care
Notes:
1. AL = 0, WL = 5, t ANPD = 4.
FIGURE 113 - TRANSITION PERIOD FOR SHORT CKE HIGH CYCLES WITH ENTRY AND EXIT PERIOD OVERLAPPING
T0 CK# CK Command EKC NOP
T1
T2
T3
T4
T5
T6
T7
T8
T9
Ta0
Ta1
Ta2
Ta3
Ta4
NOP
NOP NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
t ANPD
t XPDLL t ANPD
Short CKE HIGH transition period (RTT chan ge asynchronous or synchonous)
Indicates A Break in Time Scale
Transitionin g
Don 't Care
Notes:
1. AL = 0, WL = 5, t ANPD = 4.
LOGIC Devices Incorporated
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153
High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
ADVANCE INFORMATION
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
REVISION HISTORY
Revision
A
Engineer
DH/JM
Issue Date
07/08/2009
Description Of Change
INITIATE
LOGIC Devices Incorporated reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. LOGIC Devices does not assume any liability arising out of the application or use of any product or circuit described herein. In no event shall any liability exceed the product purchase price. Products of LOGIC Devices are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with LOGIC Devices. Furthermore, LOGIC Devices does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user.
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High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A

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